[hpc-announce] CfP: 12th Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2026) at SC26

[Bakos, Jason]

CALL FOR PAPERS
12th International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2026)

Workshop Date: Monday Morning, November 16, 2026
https://urldefense.us/v3/__http://h2rc.cse.sc.edu__;!!G_uCfscf7eWS!fiKN7jL-4nCgIo8ZrM76xKKJJl5pk-ne7QMUqzMKVAm8kLIBZq0ycvHFxCuh6JLdwVGy71WImS3853pY5wc2Yuf9$ 

Accepted papers will be indexed and published by IEEE.

Submission Deadline:  August 5, 2025 (AoE)
(10-page full papers or 2-page extended abstract, see below)

Submission link: https://urldefense.us/v3/__https://bit.ly/h2rc2026__;!!G_uCfscf7eWS!fiKN7jL-4nCgIo8ZrM76xKKJJl5pk-ne7QMUqzMKVAm8kLIBZq0ycvHFxCuh6JLdwVGy71WImS3853pY54mKU5Q1$ 

High-performance computing is entering a post-exascale era in which scalable performance is constrained
not only by peak floating-point capability, but also by power delivery, energy efficiency, cooling, data
movement, memory hierarchy, and sustained utilization of increasingly heterogeneous resources. At the
same time, HPC workloads are broadening to include coupled simulation, AI, data analytics, streaming
data, and urgent decision workflows, each with distinct requirements for precision, locality, latency,
throughput, and programmability.

Spatial and reconfigurable architectures offer a compelling path forward. FPGAs remain an important
example, enabling application-specific datapaths and communication patterns that can improve
performance and efficiency. The design space is now expanding to include AI Engine arrays,
coarse-grained reconfigurable architectures (CGRAs), dataflow and streaming processors, wafer-scale
systems, and other domain-specialized spatial fabrics. These architectures promise gains not only in
raw performance, but also in performance per watt, data-movement efficiency, and the ability to
adapt computation to diverse and evolving workloads.

Realizing this potential requires advances across the hardware/software stack. The central challenge is
how programming models, compilers, intermediate representations, placement and scheduling techniques,
runtime systems, autotuning, and performance/energy models can map full HPC applications onto
emerging spatial fabrics at scale. With this in mind, the 12th Workshop on Heterogeneous
High-performance Reconfigurable Computing brings together researchers and practitioners in HPC,
computer architecture, compilers, and heterogeneous systems to share experiences, demonstrate new
techniques, and identify future opportunities and research needs for high-performance spatial and
reconfigurable computing.

Submission Tracks and Contribution Selection

Submissions are solicited for two tracks:

Track 1: Full-length papers of 4 to 10 pages, excluding references, for oral presentation and publication
in the SC Workshop Proceedings.

Track 2: Extended abstracts / talk proposals of up to 2 pages, excluding references, for oral presentation
without publication in the SC Workshop Proceedings.

Track 1 is intended for technical papers containing substantial implementation detail, methodological
contribution, evaluation, and analysis of experimental results. Track 1 is well suited for academic, national
laboratory, and industrial authors who seek peer-reviewed archival publication in the SC Workshop
Proceedings.

Track 2 is intended for industrial contributions describing new capabilities, products, platforms, tools, or
application opportunities, as well as work-in-progress presentations from academic, national laboratory, and
industrial authors. The emphasis of Track 2 is to stimulate discussion with the workshop audience. Accepted
Track 2 extended abstracts will be made available on the workshop website but will not appear in the SC
Workshop Proceedings.

Each submission will receive at least three peer reviews by members of the technical program committee.
Using the TPC reviews, the organizing committee will select contributions for presentation based on scientific
merit, technical quality, interest, and relevance to the HPC community.

Submission Topics

Submissions are solicited that explore the state of the art in reconfigurable, spatial, and dataflow architectures
for heterogeneous high-performance computing. Relevant platforms include, but are not limited to, FPGAs, AI
Engine arrays, coarse-grained reconfigurable architectures, compiler-scheduled spatial architectures, streaming
and dataflow processors, wafer-scale systems, and emerging commercial or experimental spatial fabrics.

Submissions may consider these architectures as standalone accelerators, as components of heterogeneous
nodes, as distributed or composable compute fabrics, or as dynamically adaptable resources in larger HPC systems,
clouds, and data centers. Work investigating their integration with CPUs, GPUs, APUs, DPUs, NPUs, SmartNICs,
memory systems, networks, and storage systems is particularly welcome.

Submissions may report on theoretical or applied research, implementation case studies, benchmarks, standards,
tools, experience reports, or any other work that advances understanding of heterogeneous high-performance
reconfigurable and spatial computing. A non-exhaustive list of topics of interest includes:

(1) Performance and energy efficiency of HPC applications on FPGAs, AI Engines, CGRAs, dataflow processors,
wafer-scale systems, and other spatial architectures
(2) Compilation techniques for spatial and reconfigurable architectures, including scheduling, placement, routing,
mapping, graph lowering, autotuning, design-space exploration, MLIR/LLVM-based flows, and domain-specific compiler
frameworks
(3) Runtime systems, resource management, dynamic adaptation, and utilization-aware scheduling for heterogeneous
spatial fabrics
(4) Programming models, libraries, DSLs, and portability layers for spatial and reconfigurable computing
(5) Application studies in simulation, AI for science, sparse and irregular computation, stencils, linear algebra, signal
processing, graph analytics, compression, visualization, and data-intensive workflows
(6) System integration of spatial accelerators in HPC systems, clouds, composable infrastructures, data centers, storage
systems, and networks
(7) Performance, power, thermal, reliability, and cost modeling for heterogeneous reconfigurable and spatial systems
(8) Benchmarks, proxy applications, reproducibility, and evaluation methodologies
(9) Debugging, verification, profiling, and performance-analysis tools for spatial and reconfigurable architectures
(10) Hardware/software co-design for post-exascale HPC and AI workloads
(11) Experience reports on emerging commercial, prototype, or experimental spatial/dataflow platforms, including
lessons learned and open challenges

Detailed Submission Guidelines

Full papers (Track 1)

Authors should submit original contributions of 4 to 10 pages, excluding references, in PDF format using the SC26 Linklings
submission portal, which is also linked from the H2RC website. Submissions must be formatted using the IEEE conference
proceedings template.

H2RC uses a single-blind review process. Authors do not need to anonymize submissions.

In support of the SC reproducibility initiative, authors are strongly encouraged to include an optional Artifact Description
/ Artifact Evaluation appendix of up to 2 additional pages. This appendix does not count toward the 10-page paper limit.

Accepted Track 1 papers will be published in the SC Workshop Proceedings.

Talk proposals (Track 2)

Authors should submit a 2-page extended abstract, excluding references, in PDF format using the SC26 Linklings submission
portal. Extended abstracts must use the same formatting instructions as full papers.

Track 2 extended abstracts will be peer-reviewed and used to decide whether to assign a presentation slot. Accepted Track 2
abstracts will be made available on the workshop website but will not be included in the SC Workshop Proceedings.

AI-generated text policy

In accordance with SC26 workshop policy, the use of AI-generated text in a submitted article must be disclosed in the
acknowledgments section. Authors must identify the sections that used AI-generated text and cite the AI system used. Large
language models may be used as general-purpose writing assistance tools, but they are not eligible for authorship, and authors
remain fully responsible for the content of their submissions.

Important dates:

Submission Deadline:                                	August 5, 2026
Acceptance Notification:                            	September 4, 2026
Camera-ready Manuscripts Due:               September 25, 2026
Workshop Date:                                         	November 16, 2026
Workshop Format

H2RC is a half-day Monday morning workshop. It will consist of invited talks and presentations selected from submitted full papers
and extended abstracts.

Workshop Organizers:

Jason D. Bakos, University of South Carolina
Andrew Schmidt, AMD
Suhaib A. Fahmy, King Abdullah University of Science and Technology

-- 
Jason D. Bakos, Ph.D., Professor
Dept. of Computer Science and Engineering
Univ. of South Carolina