[hpc-announce] [CFP] RISC-V PPAM 2026 Workshop

[Roman Wyrzykowski]

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     ******        2nd PPAM Workshop on RISC-V              ******
     ******              RISC-V PPAM 2026                   ******
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     ******               in conjunction with:              ******
     ******        16TH INTERNATIONAL CONFERENCE ON         ******
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     ******                    PPAM 2026                    ******
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August 30 - September 2, 2026,
Poznan, Poland
https://urldefense.us/v3/__http://ppam.edu.pl__;!!G_uCfscf7eWS!d6jfj4ui-_zV4vgfnBXjE-1nzPrMTcmGOUkKbUtYIqm34R6SRRl51G2f68c49YpFnZTFv6-juv6NnH9ckTsBNnuP$ 

Co-located with PPAM 2026, this is the second edition of workshops
devoted to all aspects of the RISC-V technology with a special
emphasis on high-performance computing (HPC), edge computing, and AI/ML.
The first edition was successfully carried out in Ostrava on
September 9, 2024, during PPAM 2024.

BACKGROUND
==========
The goal of this workshop is to continue building the RISC-V community,
sharing the benefits of RISC-V with computer science specialists and
domain scientists. RISC-V is an open standard Instruction Set Architecture
(ISA) that enables the royalty-free development of CPUs and accelerators,
as well as the common software ecosystem. Following this community-driven
ISA standard, a very diverse set of CPUs suited to a range of workloads
has been, and continues to be, developed, alongside domain-specific
platforms. While RISC-V has already become very popular in some fields,
like embedded and edge computing, it has yet to gain traction in
general-purpose computing, including HPC and AI/M. In particular, recent
advances in RISC-V make it a more realistic proposition for HPC workloads
than ever before. An example is the vectorization extension, which provides
essential performance advantages for HPC workloads but was only
standardized in early 2022, so we are only now seeing mature CPUs that
fully implement this extension. Another milestone on the way to the wider
adoption of the RISC-V architecture in HPC is the recent ratification of
the RVA23 Profile. It is essential for software portability across many
hardware implementations and helps to avoid vendor lock-in.

By sharing the benefits of the architecture, success stories, and
techniques, the second edition of this Workshop aims to popularize RISC-V
among the PPAM community, bringing together specialists involved in
developing RISC-V hardware/software and those looking to exploit the
potential of new computer architectures in a broad spectrum of domains,
including general-purpose computing, HPC, embedded and edge computing,
AI/ML, etc.

This Workshop is organized in technical cooperation with Barcelona
Supercomputing Center, and EPCC Edinburgh, as well as with InspireSemi
and E4 Computer Engineering.

Topics of interest for the Workshop include (but are not limited to):
• RISC-V hardware/software ecosystem,
• Novel hardware and accelerators built on RISC-V,
• Tools, compilers, libraries, and techniques to support the use of
   RISC-V for HPC,
• RISC-V in general-purpose computing, HPC, AI/ML, embedded and edge
   computing,
• Porting of codes to RISC-V, including benchmarking,
• Scientific and industrial use cases and case studies that use RISC-V
• Industry papers related to RISC-V
• RISC-V in education

PAPER SUBMISSION AND PUBLICATION
================================
All rules of paper submission of the PPAM 2026 conference apply.
In particular:
• Papers will be refereed and accepted based on their scientific merit
   and relevance to the Workshop topics.
• Papers presented at the Workshop will be included in the conference
   proceedings and published by Springer in the LNCS series after the
   conference.
• Before the Workshop, abstracts of accepted papers will be posted on
   the PPAM site.
• Authors should submit papers (PDF files) using the online submission
   tool.
• Papers are not to exceed 15 pages (LNCS style).
• Alternatively, abstracts delivering original works are invited to be
   presented at the Workshop. They should be prepared according to the
   Springer LNCS format on 2 pages. Accepted abstracts will be posted on
   the workshop site before the conference.

BEST PAPER AWARD:
================
A special award including 500 euros will be awarded to the authors of
the best paper/presentation.

IMPORTANT DATES
===============
Paper due: April 30, 2026
2-page abstract due: May 7, 2026
Notification of acceptance: May 31, 2026
Workshop: August 31-September 1, 2026
Camera-ready: October 31, 2026

WORKSHOP CHAIRS
===============
Roman Wyrzykowski - Czestochowa University of Technology, Poland
roman at icis.pcz.pl

PROGRAM COMMITTEE (non-final list)
==================================
Marco Aldinucci - University of Torino, Italy
Nick Brown – EPCC, University of Edinburgh, UK
Denis Dutoit - CEA, France
Paweł Gepner - Warsaw University of Technology, Poland
Daniele Gregori - E4 Company, Italy
Andreas Herten - Forschungszentrum Juelich, Germany
Aleksandar Ilic - Technical University of Lisbon, Portugal
Filippo Mantovani - Barcelona Supercomputing Center, Spain
Manolis Marazakis - University of Crete, Greece
Norbert Meyer – Poznan Supercomputing andNetworking Center, Poland
Tomasz Olas - Czestochowa University of Technology, Poland
Olivier Perks - Rivos Inc., USA
Estela Suarez - Forschungszentrum Juelich, Germany
Pablo Vizcaino - Barcelona Supercomputing Center, Spain
Lilia Zaourar - CEA, France