[hpc-announce] [Deadline extension] Call for papers--Workshop on Computer Architecture Modeling and Simulation

Li, Ying yli81 at wm.edu
Mon Aug 28 19:27:43 CDT 2023

[Deadline Extension] Papers due: September 15, 2023


Call for papers

The 1st Workshop on Computer Architecture Modeling and Simulation (CAMS 2023)


October 28 or 29, 2023

Toronto, Canada



Simulator and performance modeling tools are the lifeblood of advancements in computer architecture research and design. They allow researchers to predict, analyze, and understand complex systems, ultimately driving forward technological innovation. Our "Computer Architecture Modeling and Simulation" workshop is dedicated to this critical field. It offers a platform for enthusiasts, researchers, and industry professionals to discuss simulator development, performance and power modeling, AI-based modeling techniques, and more. Beyond exploring technical aspects, this workshop emphasizes the necessity of creating and appreciating effective tools and standardizing methods to evaluate them. We aim to generate meaningful discussions and collaboration, fostering the development of impactful solutions and methodologies that will shape the future of computer architecture modeling and simulation.

Authors are invited to submit original research papers in the general area of computer architecture modeling and simulation. Topics include, but are not limited to:

* Simulator Development: Design, theory, implementation, and integration of simulators.

* Performance Modeling: Strategies for prediction, validation, and architectural feature impact assessment.

* Power Modeling and Simulation: Methods for power-efficient design and power-performance trade-off analysis.

* Tools and Studies Survey: Review and comparison of existing simulation tools and applications.

* Scalable Simulation Techniques: Approaches for improving simulation scalability and efficiency.

* Modeling and Simulation for Unconventional Architectures: Challenges and approaches for emerging and unconventional architectures.

* Hardware-in-the-loop Simulation: Advancements and case studies in hardware-in-the-loop validation.

* Modeling for Machine Learning (Sim4AI): Architectural considerations and models for hardware accelerators.

* AI-Based Performance Modeling Techniques (AI4Sim): Exploration of AI application in performance modeling.

* Validation Techniques: Approaches for validating simulation model accuracy.

* Human-centered Simulation Methods: User-friendly visualization, real-time monitoring, and user-centric analysis techniques.

==Important Dates==

Papers due: September 15, 2023

Author Notification: October 6, 2023

==Submission Guideline==

Full paper submissions must be in PDF format for US letter-size or A4 paper. They must not exceed 6 pages (excluding unlimited references) in standard ACM two-column conference format (review mode, with page numbers and both 9 or 10pt can be used). More concise papers with ideas clearly expressed are also welcomed. Authors can select if they want to reveal their identity in the submission. Templates for ACM format are available for Microsoft Word and LaTeX at this link. https://www.acm.org/publications/proceedings-template

We do not put the paper in the ACM or IEEE digital libraries. Therefore, the papers submitted to the event can be submitted to other venues without restrictions.

At least one author of accepted papers is expected to present in person during the event. We understand the travel difficulty of the post-pandemia era. In extreme cases, we will allow remote or pre-recorded presentations.



* Yifan Sun (William & Mary)

* Trevor E. Carlson (National University of Singapore)

--Web Chair

* Ying Li (William & Mary)

--Program Committee

* José L. Abellán (University of Murcia)

* Bobby Bruce (University of California, Davis)

* Shi Dong (Cerebras)

* Hyeran Jeon (University of California, Merced)

* Adwait Jog (University of Virginia)

* Youngsok Kim (Yonsei University)

* Daniel Wong (University of California, Riverside)

* Jieming Yin (Nanjing University of Post and Telecommunications)

* Zi Yan (NVIDIA)

* Le Xu (University of Texas Austin)

* Amir Kavyan Ziabari (AMD)

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