[hpc-announce] DEADLINE EXTENDED (7 December 2022): 5th AccML Workshop at HiPEAC 2023

Jose Cano Reyes Jose.CanoReyes at glasgow.ac.uk
Thu Dec 1 04:43:02 CST 2022

*5th Workshop on Accelerated Machine Learning (AccML) *

Co-located with the HiPEAC 2023 Conference

January 18, 2023
Toulouse, France

The remarkable performance achieved in a variety of application areas 
(natural language processing, computer vision, games, etc.) has led to 
the emergence of heterogeneous architectures to accelerate machine 
learning workloads. In parallel, production deployment, model complexity 
and diversity pushed for higher productivity systems, more powerful 
programming abstractions, software and system architectures, dedicated 
runtime systems and numerical libraries, deployment and analysis tools. 
Deep learning models are generally memory and computationally intensive, 
for both training and inference. Accelerating these operations has 
obvious advantages, first by reducing the energy consumption (e.g. in 
data centers), and secondly, making these models usable on smaller 
devices at the edge of the Internet. In addition, while convolutional 
neural networks have motivated much of this effort, numerous 
applications and models involve a wider variety of operations, network 
architectures, and data processing. These applications and models 
permanently challenge computer architecture, the system stack, and 
programming abstractions. The high level of interest in these areas 
calls for a dedicated forum to discuss emerging acceleration techniques 
and computation paradigms for machine learning algorithms, as well as 
the applications of machine learning to the construction of such systems.

*Links to the Workshop pages *
Organizers: https://accml.dcs.gla.ac.uk/

HiPEAC: https://www.hipeac.net/2023/toulouse/#/program/sessions/8030/

*Keynote speaker: Onur Mutlu (ETH Zurich) *
Title: Memory-Centric Computing

Abstract: Computing is bottlenecked by data. Large amounts of 
application data overwhelm storage capability, communication capability, 
and computation capability of the modern machines we design today. As a 
result, many key applications' performance, efficiency, and scalability 
are bottlenecked by data movement. In this lecture, we describe three 
major shortcomings of modern architectures in terms of 1) dealing with 
data, 2) taking advantage of the vast amounts of data, and 3) exploiting 
different semantic properties of application data. We argue that an 
intelligent architecture should be designed to handle data well. We show 
that handling data well requires designing architectures based on three 
key principles: 1) data-centric, 2) data-driven, 3) data-aware. We give 
several examples for how to exploit each of these principles to design a 
much more efficient and high performance computing system. We especially 
discuss recent research that aims to fundamentally reduce memory latency 
and energy, and practically enable computation close to data, with at 
least two promising novels directions: 1) processing using memory, which 
exploits analog operational properties of memory chips to perform 
massively-parallel operations in memory, with low-cost changes, 2) 
processing near memory, which integrates sophisticated additional 
processing capability in memory controllers, the logic layer of 
3D-stacked memory technologies, or memory chips to enable high memory 
bandwidth and low memory latency to near-memory logic. We show both 
types of architectures can enable orders of magnitude improvements in 
performance and energy consumption of many important workloads, such as 
graph analytics, database systems, machine learning, video processing. 
We discuss how to enable adoption of such fundamentally more intelligent 
architectures, which we believe are key to efficiency, performance, and 
sustainability. We conclude with some guiding principles for future 
computing architecture and system designs..

Bio: Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is 
also a faculty member at Carnegie Mellon University, where he previously 
held the Strecker Early Career Professorship. His current broader 
research interests are in computer architecture, systems, hardware 
security, and bioinformatics. A variety of techniques he, along with his 
group and collaborators, has invented over the years have influenced 
industry and have been employed in commercial microprocessors and 
memory/storage systems. He obtained his PhD and MS in ECE from the 
University of Texas at Austin and BS degrees in Computer Engineering and 
Psychology from the University of Michigan, Ann Arbor. He started the 
Computer Architecture Group at Microsoft Research (2006-2009), and held 
various product and research positions at Intel Corporation, Advanced 
Micro Devices, VMware, and Google. He received the Google Security and 
Privacy Research Award, Intel Outstanding Researcher Award, IEEE High 
Performance Computer Architecture Test of Time Award, NVMW Persistent 
Impact Prize, the IEEE Computer Society Edward J. McCluskey Technical 
Achievement Award, ACM SIGARCH Maurice Wilkes Award, the inaugural IEEE 
Computer Society Young Computer Architect Award, the inaugural Intel 
Early Career Faculty Award, US National Science Foundation CAREER Award, 
Carnegie Mellon University Ladd Research Award, faculty partnership 
awards from various companies, and a healthy number of best paper or 
"Top Pick" paper recognitions at various computer systems, architecture, 
and security venues. He is an ACM Fellow "for contributions to computer 
architecture research, especially in memory systems", IEEE Fellow for 
"contributions to computer architecture research and practice", and an 
elected member of the Academy of Europe (Academia Europaea). His 
computer architecture and digital logic design course lectures and 
materials are freely available on YouTube 
(https://www.youtube.com/OnurMutluLectures ), and his research group 
makes a wide variety of software and hardware artifacts freely available 
online (https://safari.ethz.ch/). For more information, please see his 
webpage at https://people.inf.ethz.ch/omutlu/.

*Topics *
Topics of interest include (but are not limited to):

- Novel ML systems: heterogeneous multi/many-core systems, GPUs, FPGAs;
- Software ML acceleration: languages, primitives, libraries, compilers 
and frameworks;
- Novel ML hardware accelerators and associated software;
- Emerging semiconductor technologies with applications to ML hardware 
- ML for the construction and tuning of systems;
- Cloud and edge ML computing: hardware and software to accelerate 
training and inference;
- Computing systems research addressing the privacy and security of 
ML-dominated systems.

*Submission *
Papers will be reviewed by the workshop's technical program committee 
according to criteria regarding the submission's quality, relevance to 
the workshop's topics, and, foremost, its potential to spark discussions 
about directions, insights, and solutions in the context of accelerating 
machine learning. Research papers, case studies, and position papers are 
all welcome.

In particular, we encourage authors to submit work-in-progress papers: 
To facilitate sharing of thought-provoking ideas and high-potential 
though preliminary research, authors are welcome to make submissions 
describing early-stage, in-progress, and/or exploratory work in order to 
elicit feedback, discover collaboration opportunities, and spark 
productive discussions.

The workshop does not have formal proceedings.

*Important Dates *
Submission deadline: December 7, 2022
Notification of decision: December 17, 2022

*Organizers *
José Cano (University of Glasgow)
Valentin Radu (University of Sheffield)
José L. Abellán (Catholic University of Murcia)
Marco Cornero (DeepMind)
Dominik Grewe (DeepMind)
Ulysse Beaugnon (Google)

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