[hpc-announce] 2nd Workshop on Heterogeneous Memory Systems (HMEM 2021)
Antonio J. Peña
antonio.pena at bsc.es
Thu May 6 13:42:14 CDT 2021
2ND WORKSHOP ON HETEROGENEOUS MEMORY SYSTEMS (HMEM 2021)
18 JUNE 2021 - Online
Collocated with ICS2021 (https://ics21.github.io/)
The 2nd Workshop on Heterogeneous Memory Systems (HMEM 2021) will be
held virtually on June 18, 9.00-13.00 EDT / 15.00-19.00 CEST.
CALL FOR PARTICIPATION
Heterogeneous memory architectures have recently emerged and
revolutionized the traditional memory hierarchy. Today’s architectures
may comprise multiple memory nodes, organized in complex non-uniform
access (NUMA) topologies, whose nodes include not just DRAM, but also
die-stacked DRAM, high-bandwidth multi-channel RAM, or persistent memory.
By combining different memory technologies, heterogeneous memory
architectures allow today’s systems to take advantage of the strengths
of each technology — namely, in terms of latency, bandwidth, capacity,
persistence or cost. As a result, applications may benefit from improved
performance, energy-efficiency, and cost trade-offs.
Still, exploiting the full potential of heterogeneous memory
architectures poses significant challenges. Since heterogeneous memory
architectures introduce dramatic disruptions to the usual memory
hierarchy assumptions that have guided decades of system and software
design, we need to rethink the full system stack to embrace the new era
of memory heterogeneity.
Following a successful inaugural edition at ICS 2020, the 2nd HMEM
workshop will serve as a forum to present and discuss ongoing research
around heterogeneous memory systems. The scope of the workshop
encompasses all the layers of system and software stack, from computer
architectures, operating system, middleware, programming models, runtime
systems, tools, to applications.
Topics of interest include, but are not limited to:
- Data allocation and placement in heterogeneous memories
- Caching for heterogeneous memories
- Software-defined far memories
- Disaggregated memory
- New memory consistency and persistency models
- Persistent data structures
- Abstractions and support for failure-atomicity in persistent memory
- Use cases and early experiences
Prospective authors must submit an extended abstract of up to 4 pages
through EasyChair. Prospective speakers are also welcome to submit
extended abstracts based on their recent publications.
This is a traditional-style workshop without formal papers or
proceedings. The authors of accepted communications will be invited to
(optionally) upload their extended abstract (PDF) for publication in the
Submission deadline: May 29, 2021 (AOE)
Acceptance notification: June 4, 2021
Joao Barreto, INESC-ID, Universidade de Lisboa
Antonio J. Peña, Barcelona Supercomputing Center (BSC)
Harald Servat, Intel
Antonio J. Peña (PhD)
Team Lead, Accelerators and Communications for HPC | Teaching and Research Staff
Sr. Researcher, Computer Sciences Department | Computer Architecture Department
Barcelona Supercomputing Center (BSC) | Universitat Politècnica de Catalunya (UPC)
Looking for job opportunities? Open positions in my team. Please contact me.
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