[hpc-announce] [Call for Participation] IA^3 2020 - 10th Workshop on Irregular Applications: Architectures and Algorithms

Tumeo, Antonino Antonino.Tumeo at pnnl.gov
Wed Nov 4 23:39:02 CST 2020

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IA^3 2020
10th Workshop on Irregular Applications: Architectures and Algorithms
November 11, 2020
Virtual Workshop
In conjunction with SC20
Sponsored by IEEE TCHPC

Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, sparse matrices, deep nets, tables, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.

Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Emerging supercomputing applications are moving towards a convergence of scientific simulation, data analytics, and learning algorithms, mixed in various ways. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years.

This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. 

10:00-10:10	Welcome and Introduction (Live)
		Antonino Tumeo (PNNL), John Feo (PNNL), Vito Giovanni Castellana (PNNL)

10:10-10:40	Keynote 1 - Research Challenges in Compiler Technology for Sparse Tensors (Live)
		Prof. Mary Hall (University of Utah)

10:40-10:50	Keynote 1 Live Q/A  - Moderator: John Feo (PNNL)
		Prof. Mary Hall (University of Utah)

10:50-11:00	Break

11:00-12:10	Session 1  (Pre-recorded videos)

		Accelerating Domain Propagation: an Efficient GPU-Parallel Algorithm over Sparse Matrices
		Boro Sofranac (Berlin Institute of Technology), Ambros Gleixner (Berlin Institute of Technology), Sebastian Pokutta 		(Berlin Institute of Technology)

		Parallelizing Irregular Computations for Molecular Docking
		Leonardo Solis-Vasquez (Technical University Darmstadt), Diogo Santos-Martins (Scripps Research Institute), 			Andreas F. Tillack (Scripps Research Institute), Andreas Koch (Technical University Darmstadt), Jérôme Eberhardt 		(Scripps Research Institute), Stefano Forli (Scripps Research Institute)

		Reducing Queuing Impact in Irregular Data Streaming Applications
		Stephen W. Timcheck (Washington University in St. Louis), Jeremy D. Buhler (Washington University in St. Louis)

		Supporting Irregularity in Throughput-Oriented Computing by SIMT-SIMD Integration (short)
		Daniel Thuerck (NEC Laboratories Europe)

12:10-12:30	Session 1 Live Q/A - Moderator: Antonino Tumeo (PNNL)

		Boro Sofranac (Berlin Institute of Technology), Leonardo Solis-Vasquez (Technical University Darmstadt), Stephen 		W. Timcheck (Washington University in St. Louis), Daniel Thuerck (NEC Laboratories Europe)

12:30-12:40	Break

12:40-13:40	Live Panel - Moderator: Vito Giovanni Castellana (PNNL)
		Scott Beamer (University of California, Santa Cruz), Michela Becchi (North Carolina State University), Angela 			Bonifati (Lyon 1 University), Roger Pearce (Lawrence Livermore National Laboratory), Anil Vullikanti (University of 		Virginia)

13:40-14:30	Lunch Break

14:30-15:00	Keynote 2: Memory Performance Optimization (Pre-recorded video)
		Dr. Nuwan Jayasena (AMD Research)

15:00-15:10	Keynote 2 Live Q/A - Moderator: Marco Minutoli (PNNL)
		Dr. Nuwan Jayasena

15:10-15:20	Break

15:20-16:30	Session 2 (Pre-recorded videos)

		DistDGL: Distributed Graph Neural Network Training for Billion-Scale Graphs
		Da Zheng (Amazon), Chao Ma (Amazon), Minjie Wang (Amazon), Jinjing Zhou (Amazon), Qidong Su (Amazon), Xiang 		Song (Amazon), Quan Gan (Amazon), Zheng Zhang (Amazon), George Karypis (Amazon)

		Labeled Triangle Indexing for Efficiency Gains in Distributed Interactive Subgraph Search
		Tahsin Reza (Lawrence Livermore National Laboratory), Matei Ripeanu (University of British Columbia), Geoffrey 		Sanders (Lawrence Livermore National Laboratory), Roger Pearce (Lawrence Livermore National Laboratory)

		Distributed Memory Graph Coloring Algorithms for Multiple GPUs
		Ian Bogle (Rensselaer Polytechnic Institute), Erik Boman (Sandia National Laboratories), Karen Devine (Sandia 			National Laboratories), Sivasankaran Rajamanickam (Sandia National Laboratories), George Slota (Rensselaer 			Polytechnic Institute)

		Performance Evaluation of the Vectorizable Binary Search Algorithms on an FPGA Platform (short)
		Zheming Jin (Argonne National Laboratory), Hal Finkel (Argonne National Laboratory)

16:30-16:50	Session 2 Live Q/A - Moderator: Antonino Tumeo (PNNL)
		Da Zheng (Amazon), Tahsin Reza (Lawrence Livermore National Laboratory), Ian Bogle (Rensselaer Polytechnic 			Institute), Zheming Jin (Argonne National Laboratory)

16:50-17:00	Thank you and closing
		Antonino Tumeo (PNNL), John Feo (PNNL), Vito Giovanni Castellana (PNNL)

Special Issue

Authors of papers accepted to the workshop will also be invited to submit extended version of their papers to a Special Issue of the journal of Parallel Computing (ParCO) on Hardware/Software Co-design for Sparse and Irregular Applications.

Submissions for the special issue with open December 1, 2020 and will close on March 1, 2021.

For more information on this special issue, please visit the special issue page and/or contact the guest co-editors, Flavio Vella (flavio.vella at unibz.it) and Antonino Tumeo (antonino.tumeo at pnnl.gov).


Antonino Tumeo (PNNL), antonino.tumeo at pnnl.gov
John Feo (PNNL), john.feo at pnnl.gov
Vito Giovanni Castellana (PNNL), vitoGiovanni.castellana at pnnl.gov

Proceedings Chair
Marco Minutoli (PNNL and WSU), marco.minutoli at pnnl.gov

Artifact Evaluation Chair
Biagio Cosenza (University of Salerno), bcosenza at unisa.it

Technical Program Committee
Nesreen Ahmed, Intel, US
Johnathan Alsop, AMD, US
Eishi Arima, University of Tokyo, JP
Scott Beamer, University of California, Santa Cruz, US
Jonathan Beard, ARM, US
Michela Becchi, North Carolina State University, US
Sanjukta Bhowmick, University of North Texas, US
Erik Boman, SNL, US
David Brooks, Harvard University, US
Prerna Budhkar, Intel, US
Aydin Buluc, LBNL, US
Anastasiia Butko, LBNL, US
Assefaw Gebremedhin, Washington State University, US
Cat Graves, HPE, US
Rajiv Gupta, University of California, Riverside, US
Peter M. Kogge, Notre Dame University, US
John Leidel, Tactical Computing Lab, US
Kamesh Madduri, Pennsylvania State University
José Moreira, IBM Research, US
Miquel Moretó, Barçelona Supercomputing Center, ES
Maxim Naumov, Facebook, US
Fanny Nina-Paravecino, Microsoft, US
Roger Pearce, LLNL, US
Keshav Pingali, University of Texas, Austin, US
Alejandro Rico, ARM, US
Jason Riedy, Georgia Tech, US 
Thomas B. Rolinger, University of Maryland, US
Kentaro Sano, RIKEN, JP 
John Shalf, LBNL, US
Shaden Smith, Microsoft, US 
Tyler Sorensen, University of California, Santa Cruz, US
Ruud van der Pas, Oracle, NL
Ana Lucia Varbanescu, University of Amsterdam, NL
Flavio Vella, Free University of Bozen, IT 

Other members TBD

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