[hpc-announce] [Call for Participation and Final Program] for the 3rd Workshop on Memory Centric High Performance Computing 2020 held in Conjunction with SC'20
yanyh15 at gmail.com
Wed Nov 4 07:37:31 CST 2020
The 3rd Workshop on Memory Centric High Performance Computing 2020
held in Conjunction with SC'20 will take place on Wednesday November
11 as a virtual event. We welcome all of you to attend and interact
with the speakers and audience.
The workshop program is available from
https://sc20.supercomputing.org/session/?sess=sess195, and from this
email in the following.
10:00am - 10:05am Welcome, by Yonghong Yan, Ron Brightwell, Maya B.
Gokhale and Xian-He Sun
10:05am - 11:05am Keynote: The 3rd Wall and the Need for Innovation in
Architectures, by Peter Kogge
Session Chair: Maya B. Gokhale
Abstract: In the past we have seen two major "walls" (memory and
power) whose vanquishing required significant advances in
architecture. This talk will discuss evidence on the emergence of a
new third wall dealing with data locality, which is prevalent in data
intensive applications where computation is dominated by memory access
& movement – not flops, Such apps exhibit large sets of often
persistent data, with little reuse during computation, no predictable
regularity, significantly different scaling characteristics, and where
streaming is becoming important. Solving such problems will take a new
set of innovations in architecture to overcome. In addition to data on
the new wall, the talk will introduce one possible technique: the
concept of migrating threads, and give evidence of its potential value
based on several benchmarks that have shown to have scaling
difficulties on conventional architectures..
Brief Bio: PETER M. KOGGE is the McCourtney Professor of Computer
Science and Engineering at the University of Notre Dame, a retired IBM
Fellow, and a founder of Emu Solutions, Inc. His research interests
are in massively parallel computing paradigms for unconventional
applications. He holds over 40 patents and is author of two books.
Prior projects included the IOP - the world’s second multi-threaded
parallel processor which flew on every Space Shuttle, EXECUBE - the
world's first multi-core processor and first processor on a DRAM chip.
His startup, Emu Solutions, has demonstrated the first scalable system
that utilizes mobile threads to attack large-scale big data and big
graph problems. In 2008, he led DARPA’s Exascale technology study
group, which resulted in a widely referenced report on exascale
computing. Dr. Kogge has received the Daniel Slotnick best paper award
(1994), the IEEE/ACM Seymour Cray award (2012), the IEEE Charles
Babbage award (2014), the IEEE Computer Pioneer award (2015), and the
Gauss best paper award (2015).
11:05am - 11:30am Break
11:30am - 1:30pm Paper Presentation, Session I - Exploiting Heterogeneous Memory
Session Chair: Ron Brightwell
11:31am - 12:00pm Awais Khan, Hyogi Sim, Sudharshan S. Vazhkudai,
Jinsuk Ma, Myeong-Hoon Oh, and Youngjae Kim; Persistent Memory Object
Storage and Indexing for Scientific Computing; presentation
12:00pm - 12:30pm T. Chad Effler, Michael R. Jantz, and Terry Jones;
Performance Potential of Mixed Data Management Modes for Heterogeneous
Memory Systems; presentation
12:30pm - 01:00pm Steffen Christgau, and Thomas Steinke; Leveraging a
Heterogenous Memory System for a Legacy Fortran Code: The Interplay of
Storage Class Memory, DRAM and OS; presentation
01:00pm - 01:30pm Yifan Qiao, Xubin Chen, Jingpeng Hao, Tong Zhang,
Changsheng Xie, and Fei Wu; Architecting Heterogeneous Memory Systems
with DRAM Technology Only: A Case Study on Relational Database;
1:30pm - 2:30pm MCHPC'20 Break
2:30pm - 2:31pm Paper Presentation, Session II - Cache Impacts and Optimizations
Session Chair: Kyle Hale
2:31pm - 3:00pm Tom Deakin, James Cownie, Simon McIntosh-Smith, Justin
Lovegrove, and Richard Smedley-Stevenson; Hostile Cache Implications
for Small, Dense Linear Solves; presentation
3:00pm - 3:30pm Neil Butcher, Stephen Olivier, and Peter Kogge; Cache
Oblivious Strategies to Exploit Multi-Level Memory on Manycore
3:30pm - 4:00pm Mohammad Alaul Haque Monil, Seyong Lee, Jeffrey S.
Vetter, and Allen D. Malony; Understanding the Impact of Memory Access
Patterns in Intel Processors; presentation
4:00pm - 4:10pm Closing Remarks by Yonghong Yan
The MCHPC'2020 Organizing Committee.
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