[hpc-announce] Call-for-Participation - Summer School on High-Performance Interconnection Networks for HPC and Datacenters in the Exascale and Big-Data Era

Wed May 24 13:16:39 CDT 2017

[Apologies if you receive multiple copies of this CFP]

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                       CALL FOR PARTICIPATION

   Summer School on High-Performance Interconnection Networks for HPC
      and Datacenters in the Exascale and Big-Data Era (HiPINEB 2017)

                27th Summer School in Computer Science
                 of the Computing Systems Department,
                     School of Computer Science,
               University of Castilla-La Mancha  (UCLM)

                     July 10-11, Albacete, SPAIN

              http://hipineb.i3a.info/summerschool2017/

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The goal of The 27th Summer School in Computer Science, organized by the Computing Systems Department, of the University of Castilla-La Mancha, Spain, is to gather and discuss in a two-day event the latest and most prominent efforts and advances, both from industry and academia, in the design and development of scalable high-performance interconnection networks, especially those oriented to meet the Exascale challenge and Big-data demands.

1) The Summer School program will incorporate technical sessions, practical hands-on, panel discussions, etc.

2) The course lessons and talks will be in English.

3) Renowned experts will participate as speakers.

4) Graduate, Master, PhD students, professors, engineers, researchers, managers, and other people both from industry and academia are encouraged to participate.

SCOPE

By the year 2023, High-Performance Computing (HPC) Systems are expected to break the performance barrier of the Exaflop (10^18 FLOPS) while their power consumption is kept at current levels (or increases marginally), what is known as the Exascale challenge. In addition, more storage capacity and data-access speed is demanded to HPC clusters and datacenters to manage and store huge amounts of data produced by software applications, what is known as the Big-Data challenge. Indeed, both the Exascale and Big-Data challenges are driving the technological revolution of this decade, motivating big research and development efforts from industry and academia. In this context, the interconnection network plays an essential role in the architecture of HPC systems and datacenters, as the number of processing or storage nodes to be interconnected in these systems is very likely to grow significantly to meet the higher computing and storage demands. Besides, the capacity of the network links is expected to grow, as the roadmaps of several interconnect standards forecast. Therefore, the interconnection network should provide a high communication bandwidth and low latency, otherwise the network becoming the bottleneck of the entire system. In that regard, many design aspects are considered when it comes to improving the interconnection network performance, such as topology, routing algorithm, power consumption, reliability and fault tolerance, congestion control, programming models, control software, etc.

LIST OF TOPICS

The list of topics covered by this summer school includes, but is not limited to, the following:

* Interconnect architectures and network technologies for high-speed, low-latency interconnects.
* Scalable network topologies, suitable for interconnecting a huge number of nodes.
* Power saving policies in the interconnect devices and network infrastructure, both at software and hardware level.
* Good practices in the configuration of the network control software.
* Network communication protocols: MPI, RDMA, MapReduce, etc.
* APIs and support for programming models.
* Routing algorithms.
* Quality of Service (QoS).
* Reliability and Fault tolerance.
* Load balancing and traffic scheduling.
* Network Virtualization.
* Congestion Management.
* Applications and Traffic characterization.
* Modeling and simulation tools.
* Performance Evaluation.
* Interfacing accelerators through the interconnect (GPUs, Xeon Phi, etc).
* Network infrastructure in distributed storage, distributed databases and Big-Data.

SPEAKERS

* Jose Duato, Technical University of Valencia, Spain
* Eitan Zahavi, Mellanox Technologies, Israel
* Pedro J. García, University of Castilla-La Mancha, Spain
* Ben Bratu, Atos/BULL, France
* Gaspar Mora, Intel Corp, Santa Clara, USA
* Holger Fröning, Ruprecht-Karls University of Heidelberg, Germany
* Bernard Metzler, IBM Zurich Research Laboratory, Zurich, Switzerland

ORGANIZERS

Francisco J. Alfaro, University of Castilla-La Mancha, Spain
Jesús Escudero-Sahuquillo, University of Castilla-La Mancha, Spain

HONORIFIC DIRECTOR

Dr. Isidro Ramos Salavert,
Full Professor of the Department of Computer Systems and Computation,
Technical University of Valencia, Spain

AGENDA

* July 10 (Room: Salón de Actos ESII)
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9:00 – 9:30 – Registration and Welcome

9:30 – 10:00 – Opening

10:00 – 11:30 – Shared Pool of Virtualized Accelerators: A Key Architectural Innovation for Power-Efficient Clusters, Jose Duato, Technical University of Valencia, Spain.

11:30 – 12:00 – Coffee Break

12:00 – 13:30 – Congestion Management for Current and Future Interconnection Networks: Challenges and Solutions, Pedro Javier Garcia, University of Castilla-La Mancha (UCLM), Spain.

13:30 – 16:00 – Lunch

16:00 – 18:30 – Practical Lab: Hands-on configuring HPC networks

18:30 – 19:00 – Coffee Break

19:00 – 20:30 – Many-core processors interfacing interconnection networks: lessons learned and possible future directions, Holger Fröning, Ruprecht-Karls University of Heidelberg, Germany.

* July 11 (Room: Salón de Actos ESII)
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9:00 – 10:30 - Efficient integration of distributed applications with high performance I/O technologies, Bernard Metzler, IBM Zurich Research Laboratory, Zurich, Switzerland.

10:30 – 11:00 – Coffee Break

11:00 – 12:30 – New trends in Data Center and HPC networks, Eitan Zahavi, Mellanox Technologies, Israel.

12:30 – 14:00 – Intel Omni-Path Fabric: Architecture and technology overview, Gaspar Mora, Intel Corp., Santa Clara, USA.

14:00 - 16:00 - Lunch

16:00 - 17:30 - Exascale fabric administration tools - BXI Software solutions, Ben Bratu, Atos/BULL.

17:30 - 18:00 - Coffee Break

18:00 - 19:30 - Panel Session. The Future of the Interconnect Technology in the Exascale and Big-Data Era
Moderator: Pedro Javier Garcia, University of Castilla-La Mancha (UCLM), Spain.
Panelists:
        - Jose Duato, Technical University of Valencia, Spain.
        - Eitan Zahavi, Mellanox Technologies, Israel.
        - Ben Bratu, Atos/BULL.
        - Bernard Metzler, IBM Zurich Research Laboratory, Zurich, Switzerland.

19:30 - 20:00 - Farewell
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REGISTRATION

Registration fee: 50€
Registration Deadline: June 30

* Foreign Attendants:

For registration of foreign attendants, the University of Castilla-La Mancha (UCLM) administration office has enabled a system to perform the payment by means of credit card. The registration link of this system is here. As the system has not been translated to English yet, you can watch this tutorial (if the quality is low, enable the full screen mode or open it in Youtube):

https://youtu.be/1PLR0tJyYBc

You will be receive a confirmation e-mail from us, once the registration is completed. UCLM will send later the attendance certificate by e-mail.

* Spanish Residents:

In order to register, Spanish residents will follow the instructions (in Spanish) provided in this link (http://cursosdeverano.uclm.es/matricula/). Further information should be requested to hipineb at dsi.uclm.es

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