[hpc-announce] DEADLINE EXTENDED: ISC 2017 P3MA WORKSHOP (Performance Portable Programming Models for Accelerators)

Sunita Chandrasekaran sunisg123 at gmail.com
Thu Mar 30 11:59:50 CDT 2017

(Keynote at P3MA workshop will be given by Prof. David E. Keyes, KAUST. See
below for details)

*Second International Workshop on Performance Portable Programming Models
for Accelerators (P^3MA)*
*June 22, 2017*
co-located with ISC 2017
June 18 - 22, Frankfurt, German

High-level programming models aim to provide scientific applications a path
onto HPC platforms with minimal loss of portability or programmer
productivity. Emerging approaches include Domain Specific Languages (DSLs),
C++ metaprogramming, directives, and runtime APIs. Using these, developers
can incrementally port their codes to heterogeneous systems, sometimes with
minimal code changes. Although these approaches attempt to introduce
abstraction without performance penalty, programming challenges remain,
with their designs, implementations, and ease-of-use on rapidly evolving
hardware and diverse memory subsystems.
Programming approaches to address these concerns are continuously being
developed within standards committees for C++, OpenCL, OpenMP, OpenACC, and
various DSLs. This workshop is designed to assess improved features of
programming models (including but not limited to directives-based and C++
library-based programming models), their implementations, and experiences
with their deployment in HPC applications.
The workshop provides a forum bringing together researchers and developers
to examine heterogeneous computing and how it has been evolving across an
increasingly diverse set of accelerated architectures. Including an invited
opening keynote address and a closing Q&A panel with all presenters, this
workshop will provide perspectives from current research and a chance for
attendees to actively participate in this quickly changing and growing area
of HPC research.
This workshop will be held on June 22, 2017, colocated with the ISC High
Performance Conference in Frankfurt, Germany (http://www.isc-hpc.com).

*Topics of interest for workshop submissions include (but are not limited

    ▪    Experience porting applications using high-level models focused on
performance portability and productivity
    ▪    Hybrid heterogeneous or many-core programming with models such as
threading, message passing, and PGAS
    ▪    Asynchronous task and event driven APIs and execution/scheduling
    ▪    Performance-portable scientific libraries for heterogeneous systems
    ▪    Experiences in implementing compilers for performance portable
programming on current and emerging architectures
    ▪    Low level communications APIs or runtimes that support accelerator
    ▪    Extensions to programming models needed to support multiple memory
hierarchies and accelerators
    ▪    Performance modeling and evaluation tools
    ▪    Power/energy studies
    ▪    Auto-tuning or optimization strategies
    ▪    Benchmarks and validation suites

* Important Deadlines:*
*Paper Submission Deadline: April 15 , 2017 *
Paper Acceptance Notification: May 14, 2017
Camera Ready Paper: June 03, 2017
Workshop: June 23rd, 2017

*Review process*
Abstracts and papers need to be submitted via Easy Chair :
We only accept paper submissions which are formatted correctly in LNCS
style (single column format) using either the LaTeX document class or Word
template. For details on the author guidelines, please refer to Springer’s
website. Incorrectly formatted papers will be excluded from the reviewing

Papers submissions are required to be within 18 pages in the above
mentioned LNCS style. This includes all figures and references.

The submissions are "single-blind", i.e. submissions are allowed to include
the author names.
All submitted manuscripts will be reviewed. The review process is not
double blind, i.e., authors will be known to reviewers. Submissions will be
judged on correctness, originality, technical strength, significance,
quality of presentation, and interest and relevance to the conference
scope. Submitted papers may NOT have appeared in or be under consideration
for another conference, workshop or journal.


*Algorithmic and Programming Model Pillars for Emerging Architectures*
Algorithmic adaptations to use next-generation computers closer to their
potential are underway. Instead of squeezing out flops – the traditional
goal of algorithmic optimality, which once served as a reasonable proxy for
all associated costs – algorithms must now squeeze synchronizations,
memory, and data transfers, while extra flops on locally cached data
represent only small costs in time and energy. After decades of programming
model stability with bulk synchronous processing, new programming models
and new algorithmic capabilities (to make forays into, e.g., data
assimilation, inverse problems, and uncertainty quantification) must
be co-designed with the hardware. We briefly recap the architectural
constraints and application opportunities.  We then concentrate on two
types of tasks each of occupies a large portion of all scientific computing
cycles: large dense symmetric/Hermitian systems (covariances, Hamiltonians,
Hessians, Schur complements) and large sparse Poisson/Helmholtz systems
(solids, fluids, electromagnetism, radiation diffusion, gravitation).  We
examine progress in porting solvers for these tasks to the hybrid
distributed-shared programming environment, including the GPU and the MIC
architectures that make up the cores of the top scientific systems on the
floor and on the books.
David Keyes is the director of the Extreme Computing Research Center at
King Abdullah University of Science and Technology, where he was a founding
dean in 2009, and an adjoint professor of applied mathematics at Columbia
University. Keyes earned his BSE in Aerospace and Mechanical Engineering
from Princeton and his PhD in Applied Mathematics from Harvard. He works at
the algorithmic interface between parallel computing and the numerical
analysis of partial differential equations.  He is a Fellow of SIAM and AMS
and has received the AMC Gordon Bell Prize and the IEEE Sidney Fernbach


*Steering Committee*
Matthias Muller, RWTH Aachen University, Germany
Barbara Chapman, Stony Brook University, USA
Oscar Hernandez, ORNL, USA
Duncan Poole, OpenACC,
Torsten Hoefler, ETH, Zurich
Michael Wong, Codeplay Software Ltd, Canada
Mitsuhisa Sato, University of Tsukuba, Japan
Michael Klemm, OpenM P
Kuan-Ching Li, Providence University, Taiwan

*Program Chair(s)*
Sunita Chandrasekaran, University of Delaware, USA <schandra at udel.edu>
Graham Lopez, ORNL, USA <lopezmg at ornl.gov>

*Program Committee *
Samuel Thibault, INRIA, University of Bordeaux, France
James Beyer, NVIDIA, USA
Wei Ding, AMD, USA
Saber Feki, King Abdullah University, Saudi Arabia
Robert Henschel, Indiana University, USA
Eric Stotzer, Texas Instruments, USA
Amit Amritkar, University of Houston, USA
Guido Juckeland, HZDR, Germany
Will Sawyer, ETH, Zurich
Sameer Shende, University of Oregon, USA
Costas Bekas, IBM, Zurich
Toni Collis, University of Edinburgh, Scotland
Adrian Jackson, University of Edinburgh, Scotland
Henri Jin, NASA, USA
Andreas Knuepfer, TU Dresden, Germany
Steven Olivier, Sandia National Laboratory, USA
Suraj Prabhakaran, TU Darmstadt, Germany
Bora Ucar, ENS De Lyon, France
Veronica Vergara Larrea, ORNL, USA
Manisha Gajbe, Intel, USA
Govind Sreekar Shenoy , University of Edinburgh, UK

Questions?  Please contact one of the program chairs.
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