[hpc-announce] Call for Participation: ICA3PP/IUCC/CSS 2016 and 7 co-located workshops

Sat Sep 3 11:11:35 CDT 2016

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*16th International Conference on Algorithms and Architectures for Parallel
Processing (ICA3PP 2016)*

*15th International Conference on Ubiquitous Computing and Communications
(IUCC 2016)8th International Symposium on Cyberspace and Security
(CSS 2016)*

Organizers:
University Carlos III, Spain
University of Granada, Spain

Venue & Dates:
Granada, Spain, December 14-16, 2016

*Co-located events*

 ICA3PP 2016  https://www.arcos.inf.uc3m.es/wp/ica3pp2016/
<http://1nvy.mj.am/link/1nvy/y6wqk7j28ip/1/2u3I6bQCIMepb_HNIU_pMQ/aHR0cHM6Ly93d3cuYXJjb3MuaW5mLnVjM20uZXMvd3AvaWNhM3BwMjAxNi8>
 IUCC 2016      https://www.arcos.inf.uc3m.es/wp/iucc2016/
 CSS 2016       https://www.arcos.inf.uc3m.es/wp/css2016/

*Keynotes*

BUILDING UP INTELLIGIBLE PARALLEL COMPUTING WORLD, Vladimir Voevodin

The computing world is changing rapidly. All devices – from mobile phones
and personal computers to high-performance supercomputers – are becoming
parallel. The huge capacity of modern supercomputers allows complex
problems, previously thought impossible, to be solved. Performance of the
best supercomputers in the world is measured in Petaflops providing
unprecedentedly powerful instruments for research. At the same time, the
efficient usage of all opportunities offered by modern computing systems
represents a global challenge and requires new knowledge, skills and
abilities, where one of the main roles belongs to understanding of key
properties of parallel algorithms. The talk will address the urgent need
for theoretical and practical technologies of an accurate and concerted
design of high performance computing systems, highly parallel algorithms,
and extreme scaled applications to be able to solve large problems using
the current and prospective generations of high performance computing
systems. The most essential concept behind these technologies is co-design
which is a very close partnership or interrelationship between all the
layers involved in the process of solving these problems on high
performance computing systems: mathematical methods, algorithms,
applications, programming technologies, runtime systems, layers of system
software and hardware. The notion of co-design is so important for HPC that
the following thesis is definitely true: “No efficient co-design
technologies, no reasonable exascale in the future”.

MAKING THE MOST OUT OF HETEROGENEOUS CHIPS WITH CPU, GPU AND FPGA, Rafael
Asenjo

Heterogeneous computing is seen as a path forward to deliver the energy and
performance improvements needed over the next decade. That way,
heterogeneous systems feature GPUs (Graphics Processing Units) or FPGAs
(Field Programmable Gate Arrays) that excel at accelerating complex tasks
while consuming less energy. There are also heterogeneous architectures
on-chip, like the processors developed for mobile devices (laptops, tablets
and smartphones) comprised of multiple cores and a GPU. More recently, some
architectures have also paired multicores along with an FPGA in the same
die. Examples of the latest are Xilinx Zync (2 cores Cortex-A9 + FPGA),
Xilinx UltraScale+ MPSoC (4 cores Cortex-A53 + GPU Mali 400 + FPGA) or
Intel HARP (12 cores Xeon + FPGA).
This talk covers hardware and software aspects of this kind of
heterogeneous architectures. Regarding the HW, we briefly discuss the
underlying architecture of some heterogeneous chips composed of
multicores+GPU and multicores+FPGA, delving into the differences between
both kind of accelerators and how to measure the energy they consume. We
also address the different solutions to get a coherent view of the memory
shared between the cores and the GPU or between the cores and the FPGA.
With respect to the SW, different heterogeneous programming models will be
introduced, paying more attention to those that are aimed at exploiting
several devices at the same time (CPU + GPU or CPU + FPGA). Again, the
different optimization techniques and the levels of parallelism that are
suitable for the GPU and for the FPGA will be identified. Finally, we
present our own proposal that tackles heterogenous execution of
applications based on the pipeline and parallel_for patterns. We discuss
our extensions to the Threading Building Blocks, TBB, pipeline and
parallel_for templates to automatically distribute the workload between the
multicore and the accelerator, taking care of the load balancing and
considering energy consumption in the scheduling policies. We evaluate the
performance and energy efficiency of the different approaches for several
heterogenous processors: Intel Ivy Bridge, Intel Haswell, Samsung Exynos 5
Octa, Xilinx Zync and Intel Broadwell + Altera Stratix V FPGA.

QUO VADIS UBIQUITOUS COMPUTING?, Pedro José Marrón

The world is changing at an extremely rapid pace and it seems impossible
even for computer scientists to keep up with the evolution of technologies.
Fifteen years ago, smart phones were just a dream and people were reluctant
to go online for many things. Nowadays, everything seems to be moving to
the virtual realm and as of today, 3 billion people have regular access to
the Internet and to communication technologies. This number is equal to the
world population in 1967. In this talk, we will look back at some of the
predictions of future computing done by “experts” in the last years and
will analyze the state of Ubiquitous Computing technologies using examples
from current research projects not with virtual entities, but with real
people in real cities.

*Workshops*

Please, see the each workshop´s page for details:

   - Supercomputing Co-Design Technology Workshop (SCDT)
   <http://1nvy.mj.am/link/1nvy/y6wqk7j28ip/2/XRF9TJU_jlvA46Xh7UTVSg/aHR0cDovL2Fnb3JhLmd1cnUucnUvU0NEVA>
   .
   - International Workshop in Theoretical Approaches to Performance
   Evaluation, Modeling and Simulation (TAPEMS)
   <http://1nvy.mj.am/link/1nvy/y6wqk7j28ip/3/WekMO2fdZ-JtprMmoFc28A/aHR0cDovL3RhcGVtcy51bmV4LmVzL3RhcGVtczIwMTYv>
   .
   - Ultrascale Computing for Early Researchers (UCER 2016)
   <http://1nvy.mj.am/link/1nvy/y6wqk7j28ip/4/EV_audEufA9SzA18CChynQ/aHR0cDovL2Rwcy51aWJrLmFjLmF0L35qdWFuL3VjZXIv>
   .
   - The 1st International Workshop on Trust, Security and Privacy for Big
   Data (BigTrust 2016)
   <http://1nvy.mj.am/link/1nvy/y6wqk7j28ip/5/EjTny2zRdvTpjZ68U31OFg/aHR0cDovL2NzZWUuaG51LmVkdS5jbi9oYnMv>
   .
   - First International Workshop on Data Locality in Modern Computing
   Systems (DLMCS 2016)
   <http://1nvy.mj.am/link/1nvy/y6wqk7j28ip/6/wBN186ntfKJJoAEYNJV_wA/aHR0cDovL3d3dy5kbG1jcy5vcmcv>
   .
   - End-to-end Service Orchestration for 5G and Beyond (En2ESO)
   <https://sites.google.com/site/en2eso16/>.
   - The 2nd workshop on Virtual Environments and Advanced Interfaces (VEAI)
   <https://sites.google.com/a/my.westminster.ac.uk/veai-2016/>.
   - Smart Ubiquitous Technology for Human Behavior Coaching (SUT4Coaching)
   <http://reset.ugr.es/SUT4Coaching/>.

*Conference Venue*

The conference will be held in the Sercotel Gran Hotel Luna de Granada. The
Sercotel Gran Hotel Luna de Granada is situated in the centre of this
historic city and is equipped to play host to all types of conferences,
conventions, shows, seminars, courses, and meetings.
Sercotel Gran Hotel Luna de Granada is 10 minutes’ walk from Granada
historic town and offers a seasonal outdoor pool and free Wi-Fi throughout.
The spacious, air-conditioned rooms at Sercotel Gran Hotel Luna de Granada
have a minibar, satellite TV and Canal Plus Fútbol. Private bathrooms come
with a bath tub and shower. Suites additionally have a seating area with a
sofa bed. Sercotel Gran Hotel Luna de Granada’s spa includes a hot tub,
turkish bath, sauna, and massage services, available for an extra cost.
Other facilities include an indoor swimming pool, paddle tennis court and a
free gym.

The Alhambra Palace is 3 km from the hotel. Granada Railway Station and the
city’s university are within 1 km of the hotel. Parking is available onsite
at an additional cost and the hotel has direct access to Granada’s A44 Ring
Road.

Sercotel Gran Hotel Luna de Granada is a 20-minute drive from Granada
Airport.

*Registration*

The registration deadlines are the following:

   - Early registration (before October 15, 2016)
   - Late/on-site registration (after October 15, 2016)

To proceed with the On-line Registration for the conference (credit card
payment also available) http://granada-en.congresoseci.com/ica3pp_iucc_
css2016.

-- 
________________________________________________________
Dr. Javier García Blas
Computer Architecture, Communications and Systems Area.
Computer Science Department. UNIVERSIDAD CARLOS III DE MADRID
Avda. de la Universidad, 30
28911 Leganés (Madrid), SPAIN
e-mail: fjblas at inf.uc3m.es
Phone:(+34) 916249143
FAX: (+34) 916249129
________________________________________________________
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