[hpc-announce] FSP 2016: CfP DEADLINE EXTENDED to July 7th (3rd Intern. Workshop on FPGAs for Software Programmers)

Markus Weinhardt m.weinhardt at hs-osnabrueck.de
Wed Jun 29 05:19:41 CDT 2016

Please accept our apologies if you receive multiple copies of this CfP.


*F I N A L   C A L L   F O R   P A P E R S*

Third International Workshop on *FPGAs for Software Programmers* (FSP 2016)
August 29, 2016, Lausanne, Switzerland

co-located with Int. Conf. on Field Programmable Logic and Applications

Extended Paper Submission Deadline: July 7, 2016

Proceedings will be published by VDE and indexed by *IEEE Xplore*


*Scope of the Workshop*
The aim of this one-day workshop is to make FPGA and reconfigurable
technology accessible to software programmers. Despite their frequently
proven power and performance benefits, designing for FPGAs is mostly an
engineering discipline carried out by highly trained specialists. With
recent progress in high-level synthesis, a first important step towards
bringing FPGA technology to potentially millions of software developers
was taken. However, to make this happen, there are still important
issues to be solved that are in the focus of this workshop.

*Topics of the FSP Workshop include, but are not limited to*
o High-level synthesis and domain-specific languages (DSLs) for FPGAs
and heterogeneous systems
o Mapping approaches and tools for heterogeneous FPGAs
o Support of hard IP blocks such as embedded processors and memory
o Development environments for software engineers (automated tool flows,
design frameworks and tools, tool interaction)
o FPGA virtualization (design for portability, hardware abstraction, etc.)
o Design automation technologies for multi-FPGA and heterogeneous systems
o Methods for leveraging (partial) dynamic reconfiguration to increase
performance, flexibility, reliability, or programmability
o Operating system services for FPGA resource management, reliability,
o Target hardware design platforms (infrastructure, drivers, portable
o Overlays (CGRAs, vector processors, ASIP- and GPU-like intermediate
o Applications (embedded computing, signal processing, bio informatics,
big data, database acceleration, etc.) using OpenCL, OpenSPL,
Vivado-HLS, etc.
o Directions for collaborations (research proposals, networking, Horizon

*Important Dates*
Submission deadline:         July 7, 2016
Notification of acceptance:  July 21, 2016
Camera-ready final version:  July 28, 2016
Workshop:                    August 29, 2016

*Submission details and publication*
Prospective authors are invited to submit original contributions (up to
eight pages) or extended abstracts describing work-in-progress or
position papers (not exceeding two pages). Details about the submission
process are available on the workshop web page
The proceedings of this workshop containing all accepted full papers
will be published by VDE-Verlag (Germany) and will be indexed by IEEE
Xplore. Every accepted paper must have at least one author registered to
the workshop by the time the camera-ready paper is due.

*General Co-Chairs*
- Andreas Koch, Technical University of Darmstadt, Germany
- Markus Weinhardt, Osnabrück University of Applied Sciences, Germany

*Proceedings Chair*
- Christian Hochberger, Technical University of Darmstadt, Germany

*Program Committee*
- Hideharu Amano, Keio University, Japan
- Jason H. Anderson, University of Toronto, Canada
- Tobias Becker, Imperial College, London, UK
- João M. P. Cardoso, University of Porto, Portugal
- Sunita Chandrasekaran, University of Delaware, USA
- Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg, Germany
- Dirk Koch, University of Manchester, UK
- Miriam Leeser, Northeastern University, USA
- Walid Najjar, University of California Riverside, USA
- Marco Platzner, University of Paderborn, Germany
- Christian Plessl, University of Paderborn, Germany
- Dan Poznanovic, Cray Inc., USA
- Olivier Sentieys, University of Rennes, France
- Dirk Stroobandt, Ghent University, Belgium
- Gustavo Sutter, Autonomous University of Madrid, Spain
- Peter Yiannacouras, Altera Corp., Canada
- Daniel Ziener, Friedrich-Alexander University Erlangen-Nürnberg, Germany

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