[hpc-announce] Fwd: HiPINEB 2015 @ IEEE Cluster 2015 - Deadline Extended

Fri May 22 14:16:38 CDT 2015

[Apologies if you received this CFP from several sources]

**** DEADLINE EXTENDED: 12 June ****

========================================================================
                              HiPINEB 2015

1st International Workshop on High-Performance Interconnection Networks
                Towards the Exascale and Big-Data Era

                 Chicago, Illinois, USA, 8 Sept 2015
                   http://www.i3a.uclm.es/HiPINEB/

     To be held in conjunction with the IEEE Cluster 2015 Conference
========================================================================

ABSTRACT

By the year 2018, High-Performance Computing (HPC) Systems are expected to
break the Exaflop performance barrier of (10^18 flops) while their power
consumption is kept at current levels (or incremented marginally), known as
the Exascale challenge. In addition, more storage capacity and data-access
speed is demanded of HPC clusters and datacenters to manage and store huge
amounts of data produced by software applications, known as the Big-Data
challenge. Consequently, the Exascale and Big-Data challenges are driving
the technological revolution of this decade, motivating significant
research and development efforts from both industry and academia. In this
context, the interconnection network plays an essential role in the
architecture of HPC systems and datacenters, as the number of processing or
storage nodes that must be interconnected in these systems is very likely
to grow significantly to meet the higher computing and storage demands.
Therefore, the interconnection network should provide high communication
bandwidth and low latency, otherwise the network will become the bottleneck
of the entire system. In that regard, many design aspects should be
considered for improving interconnection network performance, such as
topology, routing algorithm, power consumption, reliability and fault
tolerance, congestion control, programming models, control software, etc.

The main goal of this workshop is to gather and discuss, in a full-day
event, the latest and groundbreaking advances in the design, development
and configuration of scalable high-performance interconnection networks,
especially those oriented towards meeting the Exascale challenge and
Big-data demands.

All researchers and professionals, both from industry and academia, working
in the area of interconnection networks for scalable HPC systems and
Datacenters are encouraged to submit an original paper to the workshop and
to attend this event.

TOPICS OF INTEREST

The list of topics covered by this workshop includes, but is not limited
to, the following:

* High-speed, low-latency interconnect architectures and technologies
* Scalable network topologies, suitable for interconnecting a very large
number of nodes
* Power saving policies and techniques in interconnect components and
network infrastructure, at both the software and hardware levels
* Innovative configuration of the network control software
* High-performance frameworks for distributed applications: MPI, RDMA,
Hadoop, etc.
* APIs and support for programming models
* Routing algorithms
* Quality of Service (QoS)
* Reliability and Fault tolerance
* Load balancing and traffic scheduling
* Network Virtualization
* Congestion Management
* Applications and Traffic characterization
* Modeling and simulation tools
* Performance Evaluation

Note, however, that papers focused on topics that are too far from the
design, development and configuration of high-performance interconnects for
HPC systems and Datacenters (e.g., mobile networks, intrusion detection,
peer-to-peer networks or grid/cloud computing)  will be automatically
considered as out of scope and rejected without review.

PAPER SUBMISSIONS

Papers must be in PDF format and should include title, authors and
affiliations as well as the e-mail address of the contact author. Submitted
manuscripts may not exceed 8 single-spaced double-column pages using
10-point size font on 8.5x11 inch pages, including figures, tables, and
references. At least one author of the paper must be registered for the
conference workshop.
The conference style is based on IEEE (available at:
http://www.ieee.org/conferences_events/conferences/publishing/templates.html
).

Authors can buy up to four additional pages in the proceedings. The first
additional page would cost $100. The second additional page would cost
another $200 (so $300 for the two additional pages). The third additional
page would cost $300 (i.e. $600 in total for three pages), and the fourth
additional page would cost $400 (i.e. $1000 for the four additional pages).

HiPINEB manuscript submissions are managed by easyChair.  To submit a
paper, go to https://easychair.org/conferences/?conf=hipineb2015 and follow
the instructions.

PROCEEDINGS

Authors are entitled to submit original papers of high technical quality,
according to the list of topics described above. Papers will be reviewed
based on originality, novelty, technical strength, presentation quality,
correctness and relevance to the conference scope. Papers will be published
in the IEEE Cluster 2015 proceedings, which will be submitted for indexing
and inclusion in Xplore and CSDL.

SPECIAL ISSUE

Best papers among those selected for HiPINEB 2015 will be published in a
Special Issue of the Springer's Journal of Supercomputing (2013 Impact
Factor: 0.841). Further information will be provided soon.

IMPORTANT DATES

Submission Open:              3 March   2015
Paper submission:            12 June    2015 (Hard deadline)
Notification of acceptance:  15 July    2015
Camera-ready papers due:      1 August  2015
Workshop date:                8 Sep     2015

All deadlines are set at 11:59 p.m. anywhere on Earth
(cf. http://wirelessman.org/aoe.html).

WORKSHOP ORGANIZATION

Organizers:

  * Pedro Javier Garcia, University of Castilla-La Mancha, Spain
  * Jesus Escudero-Sahuquillo, Technical University of Valencia, Spain

Program Committee:

  * Ahmed Louri, University of Arizona, USA
  * Antonio Gonzalez, Technical University of Cataluña, Spain
  * Bruno Farcy, Atos, France
  * Cyriel Minkenberg, IBM, Switzerland
  * Dennis Abts, Google, USA
  * Dhabaleswar K. Panda, Ohio State University, USA
  * Elad Mentovich, Mellanox, Israel
  * Enrique Vallejo, University of Cantabria, Spain
  * Ernst Gunnar Gran, Simula Labs, Norway
  * Francisco J. Alfaro, University of Castilla-La Mancha, Spain
  * Gaspar Mora, Intel Corporation, USA
  * Holger Froning, Heidelberg University, Germany
  * John Kim, KAIST, South Korea
  * Jose Luis Sanchez, University of Castilla-La Mancha, Spain
  * Jose Miguel Montañana, Complutense University of Madrid, Spain
  * Julio Ortega, University of Granada, Spain
  * Lizhong Chen, Oregon State University, USA
  * Maria Engracia Gomez, Technical University of Valencia, Spain
  * Michihiro Koibuchi, National Institute of Informatics, Japan
  * Ola Torudbakken, Oracle, Norway
  * Pascale Rosse-Laurent, Atos, France
  * Paul Grun, Cray, USA
  * Pedro Lopez, Technical University of Valencia, Spain
  * Reetu Das, University of Michigan, USA
  * Ryan Grant, Sandia, USA
  * Scott Hemmert, Sandia, USA
  * Tor Skeie, University of Oslo, Norway

Steering Committee:

  * Jose Duato, Technical University of Valencia, Spain
  * Francisco Jose Quiles, University of Castilla-La Mancha, Spain
  * Torsten Hoefler, ETH Zurich, Switzerland
  * Timothy M. Pinkston, University of Southern California, USA

ADDITIONAL INFORMATION

For more information on HiPINEB 2015, or if you have any question, please
contact the workshop organizers at jescudero at gap.upv.es or
pedrojavier.garcia at uclm.es
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