[hpc-announce] First CFP: Int. Workshop on FPGAs for Software Programmers (FSP) at FPL 2015

[Daniel Ziener]

Please accept our apologies if you receive multiple copies of this CfP.


===============================================================================

*C A L L   F O R   P A P E R S*

Second International Workshop on *FPGAs for Software Programmers* (FSP 2015)
http://www12.cs.fau.de/ws/fsp2015/

co-located with Int. Conf. on Field Programmable Logic and Applications (FPL)
September 1, 2015, London, UK

Paper Submission Deadline: June 30, 2015

===============================================================================


*Scope of the Workshop*
The aim of this workshop is to make FPGA and reconfigurable technology
accessible to software programmers. Despite their frequently proven power and
performance benefits, designing for FPGAs is mostly an engineering discipline
carried out by highly trained specialists. With recent progress in high-level
synthesis, a first important step towards bringing FPGA technology to
potentially millions of software developers was taken. In the second edition of
the FSP workshop, we will in particular focus on success stories where FPGAs had
been exploited by software engineers.


*Topics of the FSP Workshop include, but are not limited to*
o High-level synthesis (HLS) and domain-specific languages (DSLs) for FPGAs and
  heterogeneous systems
o Mapping approaches and tools for heterogeneous FPGAs
o Support of hard IP blocks such as embedded processors and memory interfaces
o Development environments for software engineers (automated tool flows, design
  frameworks and tools, tool interaction)
o FPGA virtualization (design for portability, hardware abstraction)
o Design automation technologies for multi-FPGA and heterogeneous systems
o Methods for leveraging (partial) dynamic reconfiguration to increase
  performance, flexibility, reliability, or programmability
o Operating system services for FPGA resource management, reliability, security
o Target hardware design platforms (infrastructure, drivers, portable systems)
o Overlays (CGRAs, vector processors, ASIP- and GPU-like intermediate fabrics)
o Applications (embedded computing, signal processing, bio informatics, big
  data, database acceleration) using C/C++/SystemC-based HLS, OpenCL, OpenSPL,
  etc.
o Directions for collaborations (research proposals, networking, Horizon 2020)


*Important Dates*
Submission deadline:         June 30, 2015
Notification of acceptance:  July 31, 2015
Camera-ready final version:  August 15, 2015
Workshop:                    September 1, 2015


*Submission details and publication*
Perspective authors are invited to submit original contributions (up to six
pages) or extended abstracts describing work-in-progress or position papers
(extended abstracts should not exceed two pages). Details about the submission
process are available on the workshop web page.
Accepted papers will be included in an ePrint proceedings volume with
Open Access. Every accepted paper must have at least one author registered to
the workshop by the time the camera-ready paper is due.


*General Co-Chairs*
- Tobias Becker, Maxeler Technologies, UK
- Frank Hannig, Friedrich-Alexander University Erlangen-Nürnberg, Germany
- Dirk Koch, University of Manchester, UK
- Daniel Ziener, Friedrich-Alexander University Erlangen-Nürnberg, Germany


*Program Committee*
- Hideharu Amano, Keio University, Japan
- Jason H. Anderson, University of Toronto, Canada
- Gordon Brebner, Xilinx Inc., USA
- João M. P. Cardoso, University of Porto, Portugal
- Andreas Koch, Technical University of Darmstadt, Germany
- Miriam Leeser, Northeastern University, USA
- Gael Paul, PLDA, France
- Dan Poznanovic, Cray Inc., USA
- Dirk Stroobandt, Ghent University, Belgium
- Gustavo Sutter, Autonomous University of Madrid, Spain
- Kazutoshi Wakabayashi, NEC Corp., Japan
- Markus Weinhardt, Osnabrück University of Applied Sciences, Germany