[hpc-announce] CFP: SoC and Heterogeneous Architecture Workshop (SHAW-4) to be held with HPCA 2013

[Iyer, Ravishankar]

Dear researchers,



We are organizing the 4th Workshop on SoCs, Heterogeneous Architectures

and Workloads (SHAW-4) along with HPCA in Shenzhen, China on Feb 24, 2013.



Please find the Call for Papers below.



Please consider submitting relevant work to the workshop.



For more information on the workshop, visit http://carch.ict.ac.cn/~hpca19/shaw-4/

For more information on HPCA 2013, visit http://carch.ict.ac.cn/~hpca19/



Regards,

-Ravi, Ramesh, Raj & Tao



******************************************************************************************

    4th Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW-4)



                     Feb 24th 2013, Shenzhen, China

                    Held in conjunction with HPCA-19



                http://carch.ict.ac.cn/~hpca19/shaw-4/

******************************************************************************************



Organizing Chairs:

------------------

Ravi Iyer         Intel Labs            ravishankar.iyer at intel.com<mailto:ravishankar.iyer at intel.com>

Ramesh Illikkal   Intel Labs            ramesh.g.illikkal at intel.com<mailto:ramesh.g.illikkal at intel.com>

Raj Yavatkar      Intel                 raj.yavatkar at intel.com<mailto:raj.yavatkar at intel.com>

Tao Wang          Peking University     wangtao at pku.edu.cn<mailto:wangtao at pku.edu.cn>



Overview

--------

Computing platforms are getting smaller (e.g. handheld devices), richer (e.g. visual

computing applications) and broader (i.e. reaching the masses via smartphones and

other embedded devices). This trend is made possible by System-on-Chip (SoC) and

Heterogeneous Architectures that combine wider power/performance scaling,

combinations of high performance and ultra-low power general-purpose cores along

with a wide spectrum of domain-specific accelerators or Intellectual Property (IP)

blocks. With the recent introduction of general-purpose compute cores such as

Intel(r) Core(tm) i7 and Atom(tm) processors, these heterogeneous platforms have the potential

to run a much broader range of applications than ever before. The goal of this workshop

is to bring together academic researchers and industry practitioners to discuss future

SoC and Heterogeneous architectures, Accelerators and Workloads. The research challenges

in SoC/Heterogeneous platforms are multi-fold: (a) providing rich functionality and

wider power/performance range (b) attempting to cover a broad range of applications

that can be migrated from mainstream platforms to SoCs and Heterogeneous devices,

(c) enabling a modular architecture and design environment that improves time-to-market

and (d) providing a rich software programming environment that eases the challenge of

developing applications on a heterogeneous architecture consisting of general-purpose

cores as well as specialized accelerators.



Below is the proposed list of topics for the workshop. Topics include, but are not

restricted to, the following:



* Novel SoC/Hetero Architectures

- Different levels of Heterogeneity

- Heterogeneity in Cores, Frequency, Cache, Memory

- Power, Performance, Energy optimizations

- SoCs, CPU/GPU, CPU/GPGPU architectures

- Adaptive heterogeneity

- Ultra-Low Power Core Micro-architectures

- Fabrics / Network-on-chip

- Cache/Memory Hierarchies

- HW Support for Heterogeneity

- HW Support for Programmability

- HW Support for Modularity

- Simulation / Emulation Methodologies

* Emerging Workloads and Embedded Devices

- New Workloads (e.g. Visual computing examples such as Augmented Reality, Multi-modal

  interfaces, etc)

- Emerging embedded applications, devices and novel uses cases

- Workload Analysis for power/performance/energy optimization and acceleration

- Workload Partitioning between Heterogeneous Cores and Accelerators

- Performance Monitoring and Simulation

- Case Studies of SoC/Heterogeneous applications

* Novel Accelerator Designs

- Specialized Accelerator Architectures and Designs

- Domain-Specific Programmable/Configurable Accelerators

- Accelerator Interfaces for Programmability

- Development Environments for Accelerator Design

- System-Level integration of Accelerators



Submission Guidelines:

----------------------

Interested authors are encouraged to submit extended abstracts

(1 - 2 pages) or short papers (6 pages) by email to the organizing chairs. The deadline

for submission is Nov 30th. Final (short) papers will be due on Jan 25th, 2013 and will

be printed in a workshop proceedings made available to the workshop attendees.



Note: Best papers from SHAW-4 will be also considered for subsequent publication in IEEE

Computer Architecture Letters. More information on this will be available later.



Important Dates:

----------------

Abstract/Paper submission:    November 30 2012 23:59 PST

Author Notification:          December 21 2012

Final Paper Submission:       January  25 2013

Workshop:                     February 24 2013

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