[hpc-announce] CFP: Data-Flow Execution Models for Extreme Scale Computing (DFM 2012)
Pedro Trancoso
pedro at cs.ucy.ac.cy
Tue Jul 3 05:02:30 CDT 2012
*** Apologies if you have received multiple copies of this posting ***
CALL FOR PAPERS
SECOND WORKSHOP ON DATA-FLOW EXECUTION MODELS FOR
EXTREME SCALE COMPUTING (DFM 2012)
http://www.cs.ucy.ac.cy/dfmworkshop/
Minneapolis, MN, USA, September 23, 2012
(IN CONJUNCTION WITH PACT 2012)
*** Submission Deadline: July 29 ***
The First International workshop on “Data-Flow Models (DFM) for extreme
scale
computing” was held in Galveston Island, Texas in October 2011 in
conjunction
with PACT 2011. Its acceptance rate was 50% and it attracted the most
participants among the PACT workshop.
Its purpose is to bring together those researchers interested in novel
computational models based on Data-Flow principles of execution. The
switch to
multi-core systems has raised concurrency to the level of a major issue
if we
are to use the increasing number of cores in a chip.
In the past five decades, sequential computing dominated the computer
architecture landscape because designers were successful at building
faster and
faster computers by solely relying on improvements on fabrication
technologies
and architectural/organization optimizations. The most severe limitation
of the
sequential model, namely its inability to tolerate long memory latencies
has
slowed down the performance gains. This phenomenon is the ubiquitous Memory
Wall. While various mechanisms have been implemented to overcome the wall
(such as extremely efficient hardware prefetch support for example),
they only
add to another wall that hampers highly efficient execution of programs and
modern chip design: the Power Wall. Power considerations and heat
dissipation
issues have forced manufacturers to switch to multiple cores per chip
and thus
move into the concurrency era.
New concurrent models/paradigms are needed in order to fully utilize the
potential of Multi-core chips. The Data-flow model is a formal model
that can
handle concurrency and tolerate memory and synchronization latencies. Data-
Flow inspired systems could also be simpler and more power efficient than
conventional systems.
Recent work has shown that the Data-Flow principles can be used to develop
systems that can outperform systems based on conventional techniques.
Thus, it
is time to revisit Data-driven computation and bring it to the
Multi-core and
extreme scale computing.
DFM 2012 solicits novel papers that include but are not limited to:
. Novel Data-Flow inspired Execution models and architectures
. Functional and Single assignment based Languages.
. Strict and non-strict execution models.
. Compilers and tools for Data-Flow/Data-Driven systems.
. Hybrid Data-driven/Control-Driven systems.
. Survey papers on Data-Flow/Data-Driven systems.
. Position Papers on the Future of Data-Flow in the Multi-core era and
beyond.
Extended versions of the best papers will be published in a special issue
of the IJPP.
*** IMPORTANT DATES ***
Submission Deadline: July 29
Notification of Authors: Aug 20
*** STEERING COMMITTEE ***
Skevos Evripidou , University of Cyprus
Guang Gao, University of Delaware
Jean-Luc Gaudiot, University of California at Irvine
Vivek Sarkar, Rice University
Ian Watson, University of Manchester
*** PUBLICITY CHAIR ***
Pedro Trancoso, University of Cyprus
*** PROGRAM COMMITTEE ***
Skevos Evripidou, University of Cyprus
Guang Gao, University of Delaware
Jean-Luc Gaudiot, University of California at Irvine
Vivek Sarkar, Rice University
Ian Watson, University of Manchester
Kei Hiraki, University of Tokyo
David Abramson, Monash University
Costas Kyriacou, Frederic University
Pedro Trancoso, University of Cyprus
Kyriacos Stavrou, Intel Labs Barcelona, SP
John Feo, Pacific Northwest National Laboratory
*** PROCEDDING & WEB CHAIR ***
Natalie Masrujeh, University of Cyprus
*** SUBMISSION INFORMATION ***
DFM 2012 will accept both Full and Short papers. Full papers should be
prepared using the IEEE Proceedings format, and should be no longer than 8
pages. Short Papers should be submitted in the form of extended
abstracts (up to 4 pages).
More information about the hpc-announce
mailing list