[mpich-discuss] MPICH on intel x86_64 core2 quad + fedora 10

[Rajeev Thakur]

Does the cpi example in the examples directory run? If you do "make testing"
in the top-level mpich2 directory it will run the entire test suite in
test/mpi (takes an hour). If these programs run, the problem is likely in
your application or the way it is compiled or something like that.
 
Rajeev
 
 


  _____  

From: mpich-discuss-bounces at mcs.anl.gov
[mailto:mpich-discuss-bounces at mcs.anl.gov] On Behalf Of Dhiraj
Sent: Saturday, February 21, 2009 4:47 AM
To: mpich-discuss at mcs.anl.gov
Subject: Re: [mpich-discuss] MPICH on intel x86_64 core2 quad + fedora 10


Dear Rajeev,

I followed steps from installation guide and used MPICH2 with mentioned
configure option.
If I do I get following outputs,

# mpd & --- starts mpd
# mpdtrace
   COMB2 (hostname of my machine)
# mpdallexit 
   exits mpd

I have compiled the parallel code and run when mpd is on using following
command

# mpirun -n 4 ./BURN 

(BURN is executable file).... The program execution hangs and I have to do
``ctrl + c'' 
I get following message,

^CTraceback (most recent call last):
  File "<stdin>", line 811, in <module>
  File "<stdin>", line 374, in mpdboot
  File "<string>", line 1, in connect_ex
KeyboardInterrupt


I am having no clue about what is happening. Please help me in this regard.

Yours,
Dhiraj.



2009/2/20 Rajeev Thakur <thakur at mcs.anl.gov>


You can just follow the instructions in the MPICH2 installation guide. You
can use MPICH2 1.0.8 and configure with the option --with-device=ch3:nemesis
.
 
Rajeev


  _____  

From: mpich-discuss-bounces at mcs.anl.gov
[mailto:mpich-discuss-bounces at mcs.anl.gov] On Behalf Of Dhiraj
Sent: Thursday, February 19, 2009 11:11 PM
To: mpich-discuss at mcs.anl.gov
Subject: [mpich-discuss] MPICH on intel x86_64 core2 quad + fedora 10


Dear Sir,

I want to install MPICH library on intel x86_64 core2 quad + fedora 10 (OS).
I seek your help regarding an installation guide and ``hello_world'' program
execution guide
for this shared memory multi-core machine.

With warm regards,
Dhiraj Patil
IISc, Bangalore.



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