[MPICH] memory barriers inside ch3shm

[Darius Buntinas]

The fence operations are there to order load and store operations. 
Processors can reorder instructions which means that loads and stores 
may not occur in program order when "viewed" by another processor. 
These operations are there to force an ordering.

The sfence operation ensures that all stores prior to the operation 
complete before any stores after it, lfence ensures that all loads 
before the operation complete before any loads after it, and mfence 
ensures that all loads and stores before the operation complete before 
any loads and stores after it.

-d

On 10/31/2007 08:02 AM, Calin Iaru wrote:
> Hi,
> 
>    I looked over some details inside the shm channel and I am curios 
> about the sfence and mfence used inside the intra-node transfer 
> algorithm. Can you tell me what was the reason behind this decision?
> 
> 
> Best regards,
>    Calin
>