[hpc-announce] 2nd Workshop on Domain-Specialized FPGAs (DEADLINE EXTENDED)

[Ruthwik Reddy Sunketa]

2nd Workshop on Domain-Specialized FPGAs<https://urldefense.us/v3/__https://sites.google.com/view/domain-specialized-fpgas-2026/__;!!G_uCfscf7eWS!e4k3I-5VwznE1oYAZo29aslU4fzT85S4bDgwWnlh-ltZZBGA3FFoMI6DsHl9qQT7aYWYz8k2KvqJ-wMupAqLus-S$ >

Submissions Open: Dec 8, 2025. Submission Deadline: Jan 22, 2026. Workshop: Feb 22, 2026.

As FPGA architectures rapidly evolve beyond general-purpose fabrics, the industry and research community is moving toward domain-specialized FPGAs – from ML-centric fabrics to packet processing FPGAs, RFSoCs, emulation-oriented FPGAs, and more. Building on the success of last year’s inaugural event, the 2nd Workshop on Domain-Specialized FPGAs (co-located with ISFPGA 2026<https://urldefense.us/v3/__https://isfpga.org/__;!!G_uCfscf7eWS!e4k3I-5VwznE1oYAZo29aslU4fzT85S4bDgwWnlh-ltZZBGA3FFoMI6DsHl9qQT7aYWYz8k2KvqJ-wMupDzgnOdy$ >) will bring together researchers and practitioners from diverse domains to advance the state of domain-specialized FPGA architectures, benchmarks, and CAD tools. This workshop will provide a forum for sharing benchmarks, sparking creative discussions, and surfacing visionary directions in FPGA specialization.

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📣 Call for Benchmarks

We invite the community to contribute real-world workloads from any FPGA application domain as representative benchmarks. This effort is an attempt towards the development of community-driven benchmark suites for FPGA architecture and CAD for applications/domains that are not currently well represented in open-source benchmark suites. Requirements for submitted benchmarks:

  *   Must be open-source.

  *   Full application workloads are preferred, though kernels or microbenchmarks are welcome when appropriate.

  *   Any programming model is acceptable (RTL, HLS, or emerging languages). In case of HLS or emerging languages, the generated RTL must be submitted as well.

  *   Must be verified and usable with open-source FPGA tools (Yosys, VTR, etc).

  *   One submission can include multiple benchmarks.

Submissions should include:

  *   Benchmark code provided as a GitHub link, including a README with setup and execution instructions.

  *   A 2-page (excluding references) paper in ACM conference format, describing the benchmark, its relevance to the application domain, and methods employed for verification and open-source tool compatibility.

Benchmarks and papers do not need to be new unpublished work.

Selected benchmarks will be featured through poster flash talks and a poster session at the workshop.

👉 Submission Link: https://urldefense.us/v3/__https://cmt3.research.microsoft.com/WDSFPGA2026__;!!G_uCfscf7eWS!e4k3I-5VwznE1oYAZo29aslU4fzT85S4bDgwWnlh-ltZZBGA3FFoMI6DsHl9qQT7aYWYz8k2KvqJ-wMupO8L01Vy$ 

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📣 Call for Wild Ideas & Bold Positions

We are seeking early-stage, unconventional, and forward-looking ideas on domain-specialized FPGA architectures and CAD to spark creative dialogue and inspire new directions for the field. We welcome position or idea papers that explore speculative concepts, qualitative insights, or emerging research visions. Some guidelines are:

  *   Can be focused on architectures or CAD or applications for FPGAs.

  *   Quantitative results are not required.

Submissions should:

  *   Be 3 pages long (ACM conference format), excluding references.

  *   Include an abstract and expected impact/motivation of the idea/position.

Selected submissions will be given the opportunity for a 10-15 minute presentation, followed by an interactive discussion.

Papers do not need to be new unpublished work.

👉 Submission Link: https://urldefense.us/v3/__https://cmt3.research.microsoft.com/WDSFPGA2026__;!!G_uCfscf7eWS!e4k3I-5VwznE1oYAZo29aslU4fzT85S4bDgwWnlh-ltZZBGA3FFoMI6DsHl9qQT7aYWYz8k2KvqJ-wMupO8L01Vy$ 

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Join Us at ISFPGA 2026

If you work on FPGA architectures, CAD, or domain-driven hardware design—and especially if you have workloads, or wild new architecture and CAD ideas—we want to hear from you. Let’s shape the future of domain-specialized FPGAs together.

More details here: https://urldefense.us/v3/__https://sites.google.com/view/domain-specialized-fpgas-2026__;!!G_uCfscf7eWS!e4k3I-5VwznE1oYAZo29aslU4fzT85S4bDgwWnlh-ltZZBGA3FFoMI6DsHl9qQT7aYWYz8k2KvqJ-wMupDmlQTrV$ 

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Questions?

Contact: Aman Arora (aman.kbm at asu.edu<mailto:aman.kbm at asu.edu>), Abhishek Jain (abhishek.kumar.jain at amd.com<mailto:abhishek.kumar.jain at amd.com>), Andrew Schmidt (andrew.schmidt at amd.com<mailto:andrew.schmidt at amd.com>)