[hpc-announce] [2nd CFP} 8th WORKSHOP ON MODELS, ALGORITHMS AND METHODOLOGIES FOR HYBRID PARALLELISM IN NEW HPC SYSTEMS (MAMHYP-26)

[Roman Wyrzykowski]

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          **********************************************************
          ******      ANNOUNCEMENT AND CALL FOR PAPERS        ******
          ******                                              ******
          ******              8th WORKSHOP ON                 ******
          ******   MODELS, ALGORITHMS AND METHODOLOGIES FOR   ******
          ******      HYBRID PARALLELISM IN NEW HPC SYSTEMS   ******
          ******                 MAMHYP-26                    ******
          ******                                              ******
          ******               JOINTLY WITH                   ******
          ******       16th INTERNATIONAL CONFERENCE ON       ******
          ******  PARALLEL PROCESSING AND APPLIED MATHEMATICS ******
          ******                                              ******
          ******   Poznan, Poland, August 30 - Sept.2, 2026   ******
          ******                                              ******
          **********************************************************

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AIMS AND SCOPE
===============
MAMHYP-26 is the eight workshop in the series, after previous
editions held in Torun (2011), Warsaw (2013), Krakow (2915),
Lublin {2017), Bialystok (2019), Gdansk (2022) and Ostrava (2024),
jointly with the PPAM conferences. Despite the progress made in
the field, developing efficient algorithms for HPC systems with
multiple forms of parallelism among milions of computing units
is still a challenging problem.

More precisely, from an architectural point of view, an HPC sytem
can be described using a hybrid multi-level structure: at the
highest level, there are several systems connected among them by
geographic networks (System level); an intermediate level is
composed by the nodes in a single system communicating among them
through dedicated fast networks or high-performance switches (Node
level); at the lowest level, finally, there are several computing
elements, computing cores as well as graphic accelerators, sharing
resources in a single CPU (Core level).

These architecture levels have very different features, requiring
different algorithmic development methodologies. For such a reason,
the development of algorithms and scientific software for these
systems implies a suitable combination of several methodologies to
deal with the different kinds of parallelism corresponding to each
architectural level. The general aim is to develop hybrid and
hierarchical algorithms, able to be aware of the underlying platform.
The main problems in this field are the management of large
parallelism degrees due to several computing units, the heterogeneity
of these devices, and the combination of several kinds of parallelism
in a single algorithm. These topics are mainly investigated to gain
the so-called exascale performance and, from another side, to face new
forms of distributed computing as cloud computing, edge computing,
and their interaction with HPC.

TOPICS OF INTEREST
==================
We focus on contributions covering various topics related to Models,
Methodologies, Algorithms, and Environments to exploit all forms of
parallelism and their combination at all levels in the emerging
HPC systems to gather the current state of knowledge in the field.

Topics of interest include but are not limited to the following

- Hybrid and hierarchical based parallel algorithms
- Multi-core and many-core parallel computing, GPU computing
- Architecture-aware parallelization on HPC platforms
- Auto tuning techniques for heterogeneous and parallel environments
- Performance analysis and scalability models
- Techniques for multi-/many-core platforms, NUMA architectures,
   or accelerator components
- Task scheduling and load balancing among computing elements
- Synchronization and access to shared resources
- Multilevel cache management
- Tools and programming environments supporting efficient usage of
   multilevel parallelism
- Resources virtualization
- High Performance cloud/edge/fog computing
- Fault tolerant implementation
- Algorithms and software for high performance and low power devices
- RISC-V algorithms, software and applications

IMPORTANT DATES
================
Paper due  May 1, 2026
Notification of acceptance  May 31, 2026
Final version of the paper due November 2, 2026

WORKSHOP CHAIRS
================
Giuliano Laccetti - University of Naples Federico II (ITALY)
Marco Lapegna - University of Naples Federico II (ITALY).
Email marco.lapegna at unina.it

PAPER SUBMISSION AND PUBLICATIONS
==================================
All rules of paper submission of the PPAM conference apply.
In particular:

- Papers will be refereed and accepted on the basis of their
   scientific merit and relevance to the Workshop topics.

- Papers presented at the Workshop will be included into the
   conference proceedings and published after the conference
   by Springer in the LNCS series.

- Authors should submit papers (PDF files)  using
   the Easychair online submission tool

- Papers are not to exceed 15 pages (LNCS style)

- Final camera-ready versions of accepted papers will be
   required by November 2, 2026