[hpc-announce] International workshop on RISC-V for HPC at SCA/HPC Asia 2026 (RISCV-HPC26)

[Sandra Catalán Pallarés]

===============================================================
                           CALL FOR PAPERS

                 RISC-V for HPC (RISC-V HPC)
 Held in conjunction with SCA/HPCAsia26 on 26 January 2026

 https://urldefense.us/v3/__https://riscv.epcc.ed.ac.uk/community/workshops/hpcasia26-workshop/__;!!G_uCfscf7eWS!Zv07YJB-WAfLXfohMkSOQ95paqw5c6MyrJO8iRxEQI4AK8UL2nxHXyoY75WTEj7mHt69LECMU3kyeYRMn3mKVujwcI4$ 

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Submission deadline: 8th November 2025 (AoE)
Author Notification: 26th November 2025
Camera ready papers: TBD

This workshop will be held in conjunction with SCA/HPCAsia26 in Osaka and
will take place as a half-day event on the morning  (9:30 - 12:30) of Ja
nuary 26th, 2026.

The workshop seeks to advance the consolidation of the RISC-V community
within the field of High-Performance Computing (HPC) and to disseminate the
advantages of this technology among researchers, software developers, and
supercomputing practitioners. RISC-V, as an open-standard Instruction Set
Architecture (ISA), provides the foundation for developing CPUs without
royalty restrictions and supports the establishment of a shared software
environment. Owing to its community-driven character, the ISA has
stimulated the design of a heterogeneous range of processors, each
targeting distinct computational requirements. Although RISC-V has already
become prominent in several technological domains—marked most recently by
the shipment of its sixteenth billion core—it has not yet achieved
significant integration within HPC.

The trajectory of RISC-V, however, indicates considerable promise for
supercomputing. Should the pace of expansion observed in recent years
persist, its adoption in HPC workloads is expected to grow throughout the
present decade. Technical advances reinforce this expectation: newly
developed CPUs and accelerators based on RISC-V are beginning to
demonstrate performance capabilities far exceeding those of earlier
generations, making the architecture increasingly competitive in
high-performance contexts.

The openness and standardization of RISC-V are central to its strength.
They enable a broad and expanding community of stakeholders to contribute
to both the evolution of the ISA and the associated tooling. For HPC, this
dual role is particularly relevant. First, it provides an avenue to shape
the ISA so that it aligns with the demands of upcoming supercomputing
systems. Second, it ensures that, despite the proliferation of diverse CPU
implementations, software ecosystems—compilers, operating systems, and
libraries—tend to remain portable across platforms with limited
modification required.

This workshop is therefore positioned as a forum to connect proponents of
RISC-V in HPC with the wider supercomputing community. Through the exchange
of practical experiences, discussion of benefits, and presentation of
successful use cases, the event intends to stimulate broader recognition of
RISC-V and to foster greater participation in its ongoing development.

Call for papers and workshop topics
-----------------------------------

We welcome contributions presenting original, high-quality research as well
as ongoing work related to RISC-V in the context of HPC. Areas of relevance
for this workshop include, but are not restricted to:

* Demonstrations and case studies of RISC-V applications
* Insights gained from employing RISC-V in HPC
* Industry experiences and perspectives on RISC-V
* Adapting software and codes to RISC-V platforms
* New RISC-V-based processors and accelerators
* Methods and tools supporting RISC-V in HPC
* Updates and adaptations of HPC libraries for RISC-V
* Improvements to optimize RISC-V for HPC workloads
* Compiler and runtime developments for RISC-V
* Overview of the RISC-V ecosystem
* Forward-looking discussions on RISC-V’s role in HPC
*Other contributions related to RISC-V and HPC

Paper submission details
------------------------

We invite authors to submit original, unpublished work for consideration.
Accepted papers will be included in the SCA/HPCAsia proceedings.
Submissions must be in PDF format and should not exceed 12 pages, including
figures and references. Manuscripts must adhere to the ACM Proceedings
Style and be submitted via the EasyChair Online Submission System
<https://urldefense.us/v3/__https://easychair.org/my/conference?conf=riscvhpc26__;!!G_uCfscf7eWS!Zv07YJB-WAfLXfohMkSOQ95paqw5c6MyrJO8iRxEQI4AK8UL2nxHXyoY75WTEj7mHt69LECMU3kyeYRMn3mKTABxbU0$ >.
<https://urldefense.us/v3/__https://easychair.org/my/conference?conf=hpcmall2026__;!!G_uCfscf7eWS!Zv07YJB-WAfLXfohMkSOQ95paqw5c6MyrJO8iRxEQI4AK8UL2nxHXyoY75WTEj7mHt69LECMU3kyeYRMn3mKGg4PA-k$ >

All papers should be prepared in a single-column layout and follow the
official ACM formatting guidelines. Templates and detailed instructions for
submission can be found at
https://urldefense.us/v3/__https://www.acm.org/publications/authors/submissions__;!!G_uCfscf7eWS!Zv07YJB-WAfLXfohMkSOQ95paqw5c6MyrJO8iRxEQI4AK8UL2nxHXyoY75WTEj7mHt69LECMU3kyeYRMn3mKjQK1kps$ .

See https://urldefense.us/v3/__https://riscv.epcc.ed.ac.uk/community/workshops/hpcasia26-workshop/__;!!G_uCfscf7eWS!Zv07YJB-WAfLXfohMkSOQ95paqw5c6MyrJO8iRxEQI4AK8UL2nxHXyoY75WTEj7mHt69LECMU3kyeYRMn3mKVujwcI4$  for
further details and submission instructions

Organising committee
--------------------

* Nick Brown (EPCC at the University of Edinburgh)
* Enrique S. Quintana-Ortí (Universitat Politècnica de València)
* Sandra Catalán (Universitat Jaume I)

Programme committee
--
* Yogeshwar Sonawane (Center for Development of Advanced Computing (C-DAC))
* Ruymán Reyes (Codeplay Software / Intel)
* Akira Tsukamoto (OpenChip)
* Surendra Billa (Centre for Development of Advanced Computing (C-DAC))
* Chris Taylor (Tactical Computing Labs, LLC)
* Luc Berger-Vergiat (Sandia National Laboratories)
-- 

*Sandra Catalán Pallarés*
Departament d'Enginyeria i Ciència dels  Computadors
TI1107DD
Universitat Jaume I
Campus de Riu Sec
I-12071 Castelló de la Plana (Spain)
(+34) 964 72 *8257 - *catalans at uji.es <scatalan at ucm.es>