[hpc-announce] (Call for Papers) International workshop on RISC-V for HPC (RISCV-HPC) at HiPC 2025 - Submission Deadline Extended to Oct 17, 2025

[yogeshwars]

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================= CALL FOR PAPERS ==================
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International workshop on RISC-V for HPC (RISCV-HPC)

To be held in conjunction with the 32nd IEEE International Conference

on High Performance Computing, Data, and Analytics (HiPC 2025)
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https://urldefense.us/v3/__https://www.cdac.in/index.aspx?id=ev_HIPC__;!!G_uCfscf7eWS!Z1vgmiTvBwKve5yuta2wAzcPUnRmMVQt1aybldMLHWdL19nCEQmqnNDUS8dxrBpAo8lOKq4GHggj7nqkCDLX-HFpXbk$ 
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This workshop aims to provide a platform for researchers, hardware designers,
system software developers, toolchain maintainers, application scientists, and
integrators to exchange ideas on the role of RISC-V in HPC. The event will
feature discussions on experiences from early deployments, performance
evaluations, architectural innovations, and software ecosystem enhancements. We
particularly welcome participation from academic institutions, industry experts,
government research labs, and non-profits across India, Asia, and the global HPC
community.

By focusing on both the challenges and the potential of RISC-V for HPC, this
workshop seeks to build connections among stakeholders and promote open hardware
in supercomputing. Our goal is to inspire future architectures and solutions
that are open, flexible, and driven by community collaboration, complementing
HiPC’s mission to advance state-of-the-art HPC research.

TOPICS OF INTEREST
-------------------------------
We invite submissions of high-quality, original research results and
works-in-progress on RISC-V with a general connection to HPC. Topics of interest
for this workshop include (but are not limited to):
* Architectural features and innovations of RISC-V for HPC workloads.
* Compiler, runtime, and toolchain development for RISC-V HPC systems.
* Experiences and challenges in porting HPC applications to RISC-V.
* Benchmarking and performance evaluation of RISC-V-based HPC platforms.
* System software, including OS, virtualization, and resource management for
RISC-V clusters.
* Co-design approaches involving RISC-V CPUs, accelerators, and interconnects.
* Integration of RISC-V in heterogeneous and exascale HPC architectures.
* Opportunities for customization and specialization of RISC-V for
domain-specific HPC workloads.
* Security, reliability, and resilience considerations in RISC-V-based HPC
systems.
* Experiences from prototype deployments and testbeds involving RISC-V for HPC.
* Roadmaps, open challenges, and community efforts for advancing RISC-V in HPC.
* Efforts in standardization, ecosystem building, and community-driven
development for RISC-V HPC.

IMPORTANT DATES
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Paper submissions open:         September 1, 2025
Paper submission closes:        October 3, 2025 Extended to October 17, 2025
Author notification:                   November 6, 2025
Camera-ready papers:             November 14, 2025
Workshop date:                        December 17, 2025 (half day)

SUBMISSION GUIDELINES
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Submissions are welcome in the form of :-
* Short paper: 4 pages (including references, figures, tables)
* Full Paper: minimum 6 and up to 8 pages (including references, figures,
tables)
Submissions must be in PDF format and follow the IEEE 2-column conference style
(10-pt font on 8.5"×11" pages). The official IEEE conference templates are
available here:  https://urldefense.us/v3/__https://www.ieee.org/conferences/publishing/templates.html__;!!G_uCfscf7eWS!Z1vgmiTvBwKve5yuta2wAzcPUnRmMVQt1aybldMLHWdL19nCEQmqnNDUS8dxrBpAo8lOKq4GHggj7nqkCDLXcSyJCws$ 
<https://urldefense.us/v3/__https://www.ieee.org/conferences/publishing/templates.html__;!!G_uCfscf7eWS!Z1vgmiTvBwKve5yuta2wAzcPUnRmMVQt1aybldMLHWdL19nCEQmqnNDUS8dxrBpAo8lOKq4GHggj7nqkCDLXcSyJCws$ > . Page limits
include all contentfigures, tables, references, and appendices unless specified
otherwise.

All papers should present original, unpublished work and must not be under
review elsewhere. A single-blind peer review process will be used for
evaluation. Accepted papers will be presented at the workshop and included in
the companion proceedings of HiPC, accessible via IEEE Xplore.

At least one author of each accepted paper must register for HiPC 2025 and
present the work at the workshop to ensure inclusion in the official
proceedings.

Submission link:  https://urldefense.us/v3/__https://easychair.org/conferences?conf=riscvhpc2025__;!!G_uCfscf7eWS!Z1vgmiTvBwKve5yuta2wAzcPUnRmMVQt1aybldMLHWdL19nCEQmqnNDUS8dxrBpAo8lOKq4GHggj7nqkCDLXdfGEB48$ 
<https://urldefense.us/v3/__https://easychair.org/conferences?conf=riscvhpc2025__;!!G_uCfscf7eWS!Z1vgmiTvBwKve5yuta2wAzcPUnRmMVQt1aybldMLHWdL19nCEQmqnNDUS8dxrBpAo8lOKq4GHggj7nqkCDLXdfGEB48$ >

WORKSHOP ORGANISING COMMITTEE
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    Sanjay Wandhekar, C-DAC, India
    Ashish Kuvelkar, C-DAC, India
    Yogeshwar Sonawane, C-DAC, India
    Surendra Billa, C-DAC, India
    Nick Brown, EPCC at the University of Edinburgh, UK
    Teresa Cervero, Barcelona Supercomputing Center (BSC), Spain

WORKSHOP PROGRAM COMMITTEE
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    Nick Brown, EPCC, University of Edinburgh, UK
    Teresa Cervero, BSC, Spain,
    Filippo Mantovani, BSC, Spain
    Neel Gala, Incoresemi, India
    Daniele Gregori, E4 - Italy
    Prof. Sujay Deb, IIIT, Delhi
    Xavier Martorell, BSC, Spain
    Manolis Marazakis, FORTH, Greece
    Sanjay Wandhekar, C-DAC, India
    Ashish Kuvelkar, C-DAC, India
    Atul Bodas, C-DAC, India
    Libin T T, C-DAC, India
    Olivier Sentieys, INRIA, France

For all queries, please contact: riscvhpc2025[at]cdac[dot]in
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