[hpc-announce] "The Best of TVLSI" Webinar Series; Episode 2

[Xinfei Guo]

Join us for "The Best of TVLSI" Webinar Series; Episode 2

This talk will take place on *25 March 2025 at 12 pm EDT (+4:00 UTC)* and
will be delivered by *Prof. Luca Benini (ETH/U of Bologna)  and Tim Fischer
(ETH)*, titled, "FlooNoC: A 645-Gb/s/link 0.15-pJ/B/hop Open-Source NoC
With Wide Physical Links and End-to-End AXI4 Parallel Multistream Support"
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*Connection Details *

*Event link:*
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*Meeting ID:* 949 4902 8608
*Passcode*: 319033
*Add to your calendar: *
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Abstract
The new generation of domain-specific AI accelerators is characterized by
rapidly increasing demands for bulk data transfers, as opposed to small,
latency-critical cache line transfers typical of traditional cache-coherent
systems. In this article, we address this critical need by introducing the
FlooNoC network-on-chip (NoC), featuring very wide, fully advanced
extensible interface (AXI4) compliant links designed to meet the massive
bandwidth needs at high energy efficiency. At the transport level,
nonblocking transactions are supported for latency tolerance. In addition,
a novel end-to-end ordering approach for AXI4, enabled by a multistream
capable direct memory access (DMA) engine, simplifies network interfaces
(NIs) and eliminates interstream dependencies. Furthermore, dedicated
physical links are instantiated for short, latency-critical messages. A
complete end-to-end reference implementation in 12-nm FinFET technology
demonstrates the physical feasibility and power performance area (PPA)
benefits of our approach. Using wide links on high levels of metal, we
achieve a bandwidth of 645 Gb/s/link and a total aggregate bandwidth of 103
Tb/s for an 8×4 mesh of processors’ cluster tiles, with a total of 288
RISC-V cores. The NoC imposes a minimal area overhead of only 3.5% per
compute tile and achieves a leading-edge energy efficiency of 0.15 at 0.8.
Compared with state-of-the-art (SoA) NoCs, our system offers three times
the energy efficiency and more than double the link bandwidth. Furthermore,
compared with a traditional AXI4-based multilayer interconnect, our NoC
achieves a 30% reduction in area, corresponding to a 47% increase within
the same floorplan.

Biographies
Luca Benini holds the chair of digital Circuits and systems at ETHZ and is
Full Professor at the Università di Bologna. He received a PhD from
Stanford University. His research interests are in energy-efficient
parallel computing systems, smart sensing micro-systems and machine
learning hardware. He is a Fellow of the IEEE, of the ACM, a member of the
Academia Europaea, and of the Italian Academy of Engineering and
Technology. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg
award, the 2020 EDAA achievement Award, the 2020 ACM/IEEE A. Richard Newton
Award, the 2023 IEEE CS E.J. McCluskey Award, and the 2024 IEEE CS Open
Source Hardware contribution Award.
Tim Fischer received his BSc and MSc in “Electrical Engineering and
Information Technology” from the Swiss Federal Institute of Technology
Zurich (ETHZ), Switzerland, in 2018 and 2021, respectively. He is currently
pursuing a Ph.D. degree at ETH Zurich in the Digital Circuits and Systems
group led by Prof. Luca Benini. His research interests include scalable and
energy-efficient interconnects for both on-chip and off-chip communication.