[hpc-announce] SC'25 MEMO25 Workshop [Call for Paper]

[Ivy Peng]

MEMO ‘25 International Workshop on Memory System, Management and Optimization

  Held in conjunction with SC25, St. Louis, Missouri, USA

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IMPORTANT DATES
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* Full paper submission deadline: August 10, 2025
* Author notification: September 1, 2025
* Camera-ready deadline: September 29, 2025
* Workshop: November 16, 2025

For full workshop details, see:
https://urldefense.us/v3/__https://kth-scalab.github.io/events/memo25__;!!G_uCfscf7eWS!aCOn7EgR_l-kxDb7KnMYzP45WHqvl5m1V5uXDKMFwMOTTBkr-hr-ZqwwJZVe2EBd1aOQHBRECOAifhK-eKrF4FbR$ 

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WORKSHOP TOPICS

This workshop aims to bring together computer science and
computational science researchers, from industry, government labs and
academia, concerned with the challenges of efficiently using existing
and emerging memory systems. The term performance for memory systems
is general, to include latency, bandwidth, power consumption and
reliability from hardware memory technologies to the software stack to
impacts manifested in application performance. The topics of interest
include, but are not limited to:

* Evaluation, characterization, performance analysis, and use cases of
existing and emerging memory technologies, including non-volatile,
high-bandwidth, heterogeneous, disaggregated memories.
* Software, hardware, and co-design approaches that ease the adoption
and optimize the use of processing-in-memory and near-memory computing
technologies.
* Programming interfaces or language extensions that improve the
programmability of using existing and emerging memory technologies and
systems, heterogeneous memory system and unified memory systems.
* Compiler, runtime, and system techniques for optimizing data layout
and placement, page migration, coherence and consistency enforcement,
latency hiding and improving bandwidth utilization and energy
consumption of complex tiered memory systems.
* Enhancements or new developments in operating systems, storage and
file systems, and I/O system that address challenges of existing and
emerging memory technologies, memory hierarchies, heterogeneous memory
systems, and the blurred boundary between memory and storage.
* Tools, modeling, evaluation, and case studies of memory system
behavior and application performance that reveal the limitations and
characteristics of existing memory systems.
* Application development and optimization for new memory
architectures and technologies and experiences overcoming memory
related challenges in code development efforts.

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MEMO’25 Panel: Energy-efficient Memory Technology for maximizing
bandwidth and reducing latency
Panelists:

* Nuwan Jayasena, AMD
* Stephen Morein, Intel
* Mike O’Connor, Nvidia
* Michael James, Cerebras

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PROGRAM COMMITTEE

Gwendolyn Voskuilen (Sandia National Laboratories, USA)
Frank Hady (Intel Fellow)
Kengo Nakajima (The University of Tokyo; RIKEN, Japan)
Seyong Lee (Oak Ridge National Laboratory, USA)
Edgar A Leon (Lawrence Livermore National Laboratory, USA)
Petar Radojkovic (Barcelona Supercomputing Center (BSC); Polytechnic
University of Catalonia, Spain)
Jie Ren College of William & Mary, USA)
Ivy Peng (KTH Royal Institute of Technology, Sweden)
Maya Gokhale (Lawrence Livermore National Laboratory, USA)
Stephen L. Olivier (Sandia National Laboratories, USA)
Kyle Hale (Oregon State University, USA)

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ORGANIZERS

Maya Gokhale (Lawrence Livermore National Laboratory, USA)
Ivy Peng (KTH Royal Institute of Technology, Sweden)
Kyle Hale (Oregon State University, USA)
Stephen L. Olivier (Sandia National Laboratories, USA)
Ron Minnich (Hewlett Packard Enterprise, USA)