[hpc-announce] Call for Participation: Thirty-Third IEEE Heterogeneity in Computing Workshop (HCW)

[Hari Subramoni]

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                          Call For Participation

        Thirty-Third IEEE Heterogeneity in Computing Workshop (HCW)

                   to be held in conjunction with
                       IPDPS 2024, May 27, 2024
                       San Francisco, California

                         https://urldefense.us/v3/__https://hcw-ipdps.org/__;!!G_uCfscf7eWS!caNPN8LNP1VLFv8Tjqj5_szhQ7koexiVi6ZkDmtafRnZ0pjNkCw-24xRUTgkKFEQYJ6TjCw2OBivxmqxlC5nRD_vqMh7$ 
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The thirty-third Heterogeneity in Computing Workshop (HCW)
will be held at the Hyatt Regency San Francisco, San
Francisco, California, on May 27, 2024. In conjunction with
the 38th IEEE International Parallel and Distributed Processing
Symposium (IPDPS 2024). This is an in-person workshop requiring
prior registration.

HCW is sponsored by the IEEE Computer Society through the
Technical Committee on Parallel Processing (TCPP)

All times indicated on this page are in the
Pacific Daylight Time (UTC-7) time zone.

The full program is available below as well as on our program
webpage - https://urldefense.us/v3/__https://hcw-ipdps.org/program__;!!G_uCfscf7eWS!caNPN8LNP1VLFv8Tjqj5_szhQ7koexiVi6ZkDmtafRnZ0pjNkCw-24xRUTgkKFEQYJ6TjCw2OBivxmqxlC5nREulAf5A$ 

Session 1: Introductions and Keynote Presentation (8:45-10 am)

Session Chairs: DK Panda (The Ohio State University, US), Hari Subramoni
(The Ohio State University, US), and Kamesh Madduri (Penn State, US)

Yale Patt, Professor and the Ernest Cockrell, Jr. Centennial Chair in
Engineering at The University of Texas at Austin, will deliver the HCW 2024
keynote.

Title: Hetero: Where we’ve been, Where we are, and What Next?

Abstract: My first connection with hetero was back in my
assembly language days on the PDP 11/60 with DEC’s EMT
instruction which allowed users to design functions by
writing their own microcode that appropriately manipulated
the data path. Even then, there were mostly naysayers
objecting to the extra challenges in repurposing the data
path at the accompanying extra expense. In their view, the
data path had one fixed use. I never bought into that in the
same way that I think having eleven quarterbacks on the
field makes no sense to me. Later, when chip multiprocessors
became the sine qua non of microarchitecture, they insisted
on homogeneous processors since hetero meant hiring extra
design teams. I remember a panel I was on at HiPEAC in 2010
where my fellow panelists all agreed homogeneous processors
was the only thing that made sense economically. We have
successfully overcome that nonsense, and in fact pretty much
everyone now agrees that future chips will make abundant use
of accelerators. In my view the obvious next step is to make
the microarchitectures heterogeneous and turn those
structures over to the compiler to allow their effective
use. Again the pushback is, “No, that will get rid of
portability, and no company will ever allow that…for obvious
reasons.” My answer: “Economics be damned!” In this talk, I
hope to put hetero in perspective and discuss why
portability is not always the right answer.


Bio: Yale Patt is a teacher at the The University of Texas
at Austin, where he still enjoys teaching freshmen, seniors,
and graduate students, doing research, and consulting more
than 60 years after first getting involved with computer
technology. He earned obligatory degrees from reputable
universities, and has received more than enough awards for
his research and teaching. More information is available on
his website users.ece.utexas.edu/~patt for those who are
interested.

Break (10-10:30 am)

Session 2: Research Papers (10:30 am-12 pm)
Session Chair: Anne Benoit (École Normale Supérieure de Lyon, FR)

Performance Portability of the Chapel Language on Heterogeneous
Architectures

Josh Milthorpe (Oak Ridge National Laboratory, US /
Australian National University, AU), Xianghao Wang
(Australian National University, AU), Ahmad Azizi
(Australian National University, AU)

Towards dynamic autotuning of SpMV in CUSP library

Miroslav Demek (Masaryk University, CZ), Jiri Filipovic
(Masaryk University, CZ)

A Runtime Manager Integrated Emulation Environment for Heterogeneous SoC
Design with RISC-V Cores

H. Umut Suluhan (The University of Arizona, US), Serhan
Gener (The University of Arizona, US), Alexander Fusco (The
University of Arizona, US), Joshua Mack (The University of
Arizona, US), Ismet Dagli (Colorado School of Mines, US),
Mehmet Belviranli (Colorado School of Mines, US), Cagatay
Edemen (Ozyegin University, TR), Ali Akoglu (The University
of Arizona, US)

Dynamic Tasks Scheduling with Multiple Priorities on Heterogeneous
Computing Systems

Hayfa Tayeb (Inria/University of Bordeaux, FR), Bérenger
Bramas (Inria/University of Strasbourg, FR), Mathieu Faverge
(Inria/University of Strasbourg, FR), Abdou Guermouche
(Inria/University of Bordeaux, FR)

Lunch break (12-1:30 pm)

Session 3: Research Papers (1:30-3 pm)
Session Chair: Ali Akoglu (The University of Arizona, US)

PSyGS Gen A Generator of Domain-Specific Architectures to Accelerate Sparse
Linear System Resolution

Niccolò Nicolosi (Politecnico di Milano, IT), Francesco
Renato Negri (Politecnico di Milano, IT), Francesco Pesce
(Politecnico di Milano, IT), Francesco Peverelli
(Politecnico di Milano, IT), Davide Conficconi (Politecnico
di Milano, IT), Marco Domenico Santambrogio (Politecnico di
Milano, IT)

Toward a Holistic Performance Evaluation of Large Language Models Across
Diverse AI Accelerators

Murali Emani (Argonne National Laboratory, US), Sam Foreman
(Argonne National Laboratory, US), Varuni Sastry (Argonne
National Laboratory, US), Zhen Xie (State University of New
York, Binghamton, US), Siddhisanket Raskar (Argonne National
Laboratory, US), William Arnold (Argonne National
Laboratory, US), Rajeev Thakur (Argonne National Laboratory,
US), Venkatram Vishwanath (Argonne National Laboratory, US),
Michael E. Papka (Argonne National Laboratory, US), Sanjif
Shanmugavelu (Groq, US), Darshan Gandhi (SambaNova, US), Dun
Ma (SambaNova, US), Kiran Ranganath (SambaNova, US), Rick
Weisner (SambaNova, US), Jiunn-yeu Chen (Intel Habana, US),
Yuting Yang (Intel Habana, US), Natalia Vassilieva
(Cerebras, US), Bin C. Zhang (Cerebras, US), Sylvia Howland
(Cerebras, US), Alexandar Tsyplikhin (Graphcore, US)

IRIS: Exploring Performance Scaling of the Intelligent Runtime System and
its Dynamic Scheduling Policies

Beau Johnston (Oak Ridge National Laboratory, US), Narasinga
Rao Miniskar (Oak Ridge National Laboratory, US), Aaron
Young (Oak Ridge National Laboratory, US), Mohammad Alaul
Haque Monil (Oak Ridge National Laboratory, US), Seyong Lee
(Oak Ridge National Laboratory, US), Jeffrey S. Vetter (Oak
Ridge National Laboratory, US)

Heterogeneous Hyperthreading Architecture for Homogeneous Workloads

Mingxuan He (Purdue University / Futurewei Technologies,
US), Fangping Liu (Futurewei Technologies, US), Sang Wook
Stephen Do (Futurewei Technologies, US)

Break (3-3:30 pm)

Session 4: Panel and Closing Remarks (3:30-5 pm)

Impact of LLMs and Generative AI on Future Heterogeneous Systems?

Panel Moderator: Anne C. Elster (Norwegian University of Science and
Technology, NO)

Panelists: Fredrik Kjolstad (Stanford University, US),
Charles Leiserson (Massachusetts Institute of Technology,
US), DK Panda (The Ohio State University, US), Yale Patt
(The University of Texas at Austin, US)

Closing Remarks

DK Panda (The Ohio State University, US) and Hari Subramoni (The Ohio State
University, US)

Best,
DK Panda (The Ohio State University, US) and Hari Subramoni (The Ohio State
University, US)
Co-Chairs HCW'24