[hpc-announce] CfP: 10th Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC 2024) at SC24

[Bakos, Jason]

CALL FOR PAPERS
Tenth International Workshop on
Heterogeneous High-performance Reconfigurable Computing (H2RC 2024)

Workshop Date:  Half Day Friday, November 22

https://urldefense.us/v3/__http://h2rc.cse.sc.edu__;!!G_uCfscf7eWS!fGZmg_4yyKgSV2ECGICihlga0cLDLDHZ8NLL-SkTYUUG0wtVdWjVcf_RFumzb_1vY3r_vMz-t0WDfPHyAWVWN8p3$ 

Accepted papers will be indexed and published by IEEE.

Submission Deadline:  August 7, 2024 (AoE)
(8-page full papers or 2-page extended abstract, see below)

Submission link: https://urldefense.us/v3/__https://bit.ly/h2rc2024__;!!G_uCfscf7eWS!fGZmg_4yyKgSV2ECGICihlga0cLDLDHZ8NLL-SkTYUUG0wtVdWjVcf_RFumzb_1vY3r_vMz-t0WDfPHyAW6eGroM$ 

As conventional von-Neumann architectures are suffering from rising power
densities, we are facing an era with power, energy efficiency, and cooling
as first-class constraints for scalable HPC. FPGAs can tailor the hardware
to the application, avoiding overheads and achieving higher hardware
efficiency than general-purpose architectures. Leading FPGA manufacturers
have recently made a concerted effort to provide a range of higher-level,
easier-to-use high-level programming models for FPGAs, and much of the work
in FPGA-based deep learning is built on these frameworks.

Such initiatives are already stimulating new interest within the HPC community
around the potential advantages of FPGAs over other architectures. With this
in mind, this workshop, now in its ninth year, brings together HPC and
heterogeneous computing researchers to demonstrate and share experiences on
how newly-available high-level programming models are already empowering HPC
software developers to directly leverage FPGAs and to identify future
opportunities and needs for research in this area.

Submission Tracks and Contribution Selection

Submissions are solicited for two tracks:

Track 1: Full-length papers (8 pages, excluding references)
for oral presentation and publication in proceedings archived by IEEE.

Track 2: Extended abstracts / talk proposals (2 pages, excluding references)
oral presentation without publication.

Track 1 is targeted for technical papers containing a high level of
implementation detail and analysis of experimental results.  Track 1 is suited
for members of the academic and national lab community who prefer to have
their work peer-reviewed, indexed, and archived by IEEE.

Track 2 is targeted for industrial contributions that describe new
capabilities and opportunities offered by emerging technologies and products,
or work-in-progress presentations by the academic and national lab community.
The emphasis of this track is to initiate a discussion with the audience.
These extended abstracts will be made available on the conference website.

All submissions are peer-reviewed and evaluated by at least three members of
our technical program committee (TPC).  From the TPC evaluation of each
submission, the organizing committee will select papers for presentation based
on a criteria that is *equally weighted* between scientific merit and level of
interest and relevance to the HPC community.

Submission Topics

Submissions are solicited that explore the state of the art in the use of
FPGAs in heterogeneous high-performance compute architectures and, at a system
level, in data centers and supercomputers. FPGAs may be considered from either
or both the distributed, parallel and composable fabric of compute elements or
from their dynamic reconfigurability. Submissions investigating the use of
FPGAs in combination with other devices such as CPU/GPU/APU/DPU are particularly
welcomed.

Submissions may report on theoretical or applied research, implementation case
studies, benchmarks, standards, or any other area that promises to make a
significant contribution to our understanding of heterogeneous
high-performance reconfigurable computing and help to shape future research
and implementations in this domain. A non-comprehensive list of potential
topics of interest is given below:

1.	Use of FPGAs to improve performance or efficiency of HPC or data center applications 
2.	System integration of FPGAs in clouds and distributed HPC systems
3.	Leveraging reconfigurability
4.	Benchmarks
6.	Programming languages, tools, and frameworks
7.	Future-gazing

Submission Guidelines

Full papers (Track 1)

Authors should submit original contributions of up to 8 pages (excluding
references) in PDF format using the SC24 Linklings portal
(https://urldefense.us/v3/__https://submissions.supercomputing.org__;!!G_uCfscf7eWS!fGZmg_4yyKgSV2ECGICihlga0cLDLDHZ8NLL-SkTYUUG0wtVdWjVcf_RFumzb_1vY3r_vMz-t0WDfPHyAcRXMrr7$ ), which is also linked from the H2RC
website (https://urldefense.us/v3/__https://h2rc.cse.sc.edu__;!!G_uCfscf7eWS!fGZmg_4yyKgSV2ECGICihlga0cLDLDHZ8NLL-SkTYUUG0wtVdWjVcf_RFumzb_1vY3r_vMz-t0WDfPHyAUneqgfa$ ). Submissions must be formatted as
single-spaced, double-column, 8 US letter pages without page numbers following
the IEEE conference proceedings format, including figures and tables. H2RC
uses a single blind review process. We support the SC reproducibility
initiative and highly encourage authors to add an artifact description/
artifact evaluation appendix of up to 2 additional pages to their paper. All
accepted papers will be published in the IEEE Computer Society digital library.

Talk proposals (Track 2)

To apply for a talk authors should submit a 2-page extended abstract. The
extended abstract will be peer-reviewed and used for deciding on the
acceptance of a presentation assignment of a presentation slot, but will be
published only on the workshop website but not in the proceedings. The
papers shall follow the same formatting instructions as the full papers and
have also to be submitted using the Linklings system.

Important dates:

Submission Deadline: August 7
Acceptance Notification: September 6
Camera-ready Manuscripts Due: September 27
Workshop Date: November 22

Workshop Format

H2RC is a half-day Friday workshop.  It will be comprised of:

- Keynote and invited talks
- Talks selected among paper submissions

Workshop Organizers:

Jason D. Bakos, University of South Carolina
Franck Capello, Argonne National Lab
Torsten Hoefler, ETH Zurich
Ken O'Brien, AMD
Christian Plessl, Paderborn University
Melissa Crawley Smith, Clemson University

-- 
Jason D. Bakos, Ph.D., Professor
Dept. of Computer Science and Engineering
Univ. of South Carolina