[hpc-announce] [Final Extension] SC24 Workshop on Memory System, Management and Optimization - Aug 09 AOE

[Ivy Peng]

MEMO24 - International Workshop on Memory System, Management and
Optimization will be held in conjunction with SC 24 in Atlanta, GA.

IMPORTANT DATES
* Full paper submission deadline: August 09, 2024 (AoE)
* Author notification: September 06, 2024 (AoE)
* Camera-ready deadline: September 27, 2024 (AoE)
* Workshop: November 17, 2024 (AoE)

SUBMISSION
Login to SC24 submission site https://urldefense.us/v3/__https://submissions.supercomputing.org__;!!G_uCfscf7eWS!e66xSIb3cJMtps-6P6qXS9TTynZhPUhIqEbcBU9RqbrneKqx-DbQZ5_EEKFnpz629CJKu9QaiUOaX-GxPlF1oZTK$ ,
click ‘Make a New Submission’, choose MEMO (MCHPC). For SC24, IEEE is
the SC proceeding publisher. Submissions must use the template of IEEE
conference proceedings: two-column, US letter. The minimum number of
pages is 5 pages, including references, and there is no upper limit of
pages.

For more details, see https://urldefense.us/v3/__https://kth-scalab.github.io/events/memo24__;!!G_uCfscf7eWS!e66xSIb3cJMtps-6P6qXS9TTynZhPUhIqEbcBU9RqbrneKqx-DbQZ5_EEKFnpz629CJKu9QaiUOaX-GxPg-L6NzI$ 

WORKSHOP TOPICS
This workshop aims to bring together computer science and
computational science researchers, from industry, government labs and
academia, concerned with the challenges of efficiently using existing
and emerging memory systems. The term performance for memory systems
is general, which includes latency, bandwidth, power consumption and
reliability from the aspect of hardware memory technologies to how it
is manifested in the application performance. The topics of interest
include, but are not limited to:

* Evaluation, characterization, performance analysis, and use cases of
emerging memory technologies, including non-volatile memories,
high-bandwidth memory, heterogeneous memory, disaggregated memory,
etc.

* Software, hardware, and co-design approaches that ease the adoption
and optimize the use of processing-in-memory and near-memory computing
technologies.

* Programming interfaces or language extensions that improve the
programmability of using emerging memory technologies and systems,
heterogeneous memory system and multi-dimensional data, and unified
memory
systems.

* Compiler, runtime, and system techniques for optimizing data layout
and placement, page migration, coherence and consistency enforcement,
latency hiding and improving bandwidth utilization and energy
consumption of heterogeneous memory systems.

* Enhancement or new development for operating systems, storage and
file systems, and I/O system that address challenges of existing and
emerging memory technologies, heterogeneous memory systems, and the
blurred boundary between memory and storage.

* Tools, modeling, evaluation, and case study of memory system
behavior and application performance that reveals the limitations and
characteristics of existing memory systems.

* Application development and optimization for new memory architecture
and technologies and those overcome memory related challenges in their
problems.

ORGANIZING COMMITTEE
- Ron Brightwell (Sandia National Laboratories, USA)
- Ivy Peng (KTH Royal Institute of Technology, Sweden)
- Kyle Hale (Illinois Institute of Technology, USA)
- Maya Gokhale (Lawrence Livermore National Laboratory, USA)

PROGRAM COMMITTEE
- Jeff Vetter (Oak Ridge National Laboratory, USA)
- Jason Lowe-Power (University of California, Davis; Lawrence Berkeley
National Laboratory, USA)
- Thaleia Dimitra Doudali (IMDEA Software Institute, Spain)
- Seyong Lee (Oak Ridge National Laboratory, USA)
- Gwendolyn Voskuilen (Sandia National Laboratory, USA)
- Jie Ren (College of William & Mary, USA)
- Petar Radojkovic (Barcelona Supercomputing Center (BSC); Polytechnic
University of Catalonia, Spain)
- Shirley Moore (University of Texas, El Paso, USA)
- Christian Pinto (IBM, Ireland)