[hpc-announce] [CFP] IA^3 2024: 14th SC Workshop on Irregular Applications: Architectures and Algorithms

[Tumeo, Antonino]

 [Please accept our apologies for multiple postings.]

!!!!! NEW: DEADLINE EXTENDED !!!!!
!!!!! NEW: SPECIAL SUBTOPIC ON DYNAMIC GRAPHS AND DATA STRUCTURES ANNOUNCED !!!!!

IA^3 2024
14th Workshop on Irregular Applications: Architectures and Algorithms
https://urldefense.us/v3/__https://hpc.pnl.gov/IA3/__;!!G_uCfscf7eWS!YsDcAIOZQq8GY6M8ex0MDkR0K-m30wKpPlAhjDutsWzoCqJ3fJjGJM7lPCAG3_FP4xsJ1Q3BYr4gvvCDObWfb5eK2PkiLgNnuQ$ 
November 18, 2024
Atlanta, GA
In conjunction with SC24

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CALL FOR PAPERS
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Emerging data-intensive, supercomputing applications are moving towards a convergence of scientific simulations, data analytics, and learning algorithms. Many of the components of these applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. In processing massive sets of unstructured data, the components often execute many irregular, fine-grain accesses and synchronization events. Since current high-performance programming models, runtimes, and architectures rely on regular task graphs, bulk synchronous communications and high temporal and spatial data locality to reduce operational latencies, it is difficult to express irregular applications in current HPC programming models and scale performance on current supercomputing machines. Development of improved programming and execution models that address the issues of irregular applications is critical to solving the data challenges in large-scale science and data analysis.
 This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system architecture, network, languages and libraries, runtimes, compilers, algorithms, and performance studies.
 Special subtopic: new for this year, the workshop will also host a special subtopic focused on dynamic graphs. This subtopic invites experts from various disciplines to share insights and advancements in the field of dynamic network analysis, looking to address  innovative methods, applications, and challenges related to large dynamic graphs.
 Topics of interest, of both theoretical and practical significance, include but are not limited to:
 - Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor, AI/ML accelerators), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors 
- Network architectures and interconnects including high-radix and optical networks 
- Novel memory architectures and designs (including processors-in memory) 
- Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing) 
- Modeling, simulation, and evaluation of novel architectures with irregular workloads 
- Languages and programming models for irregular workloads
- Library and runtime support for irregular workloads
- Compiler and analysis techniques for irregular workloads
- Innovative algorithmic techniques for irregular workloads
- Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.)
- Impact of irregularity on machine learning approaches (e.g., graph neural networks, large language models)
- Parallelization techniques and data structures for irregular workloads
- Data structures combining regular and irregular computations (e.g., attributed graphs)
- Approaches for managing massive unstructured datasets (including streaming data) 
- High performance data analytics applications (including graph databases and solutions that combine graph algorithms with machine learning)
- Applications that integrate scientific simulation, data analytics, and learning, and require efficient execution of irregular workloads
- Hardware and software platforms, parallel algorithms, benchmarking, applications for dynamic graphs and dynamic graph neural networks
 The workshop welcomes regular paper submissions, papers describing work-in-progress or incomplete but sound, as well as innovative ideas related to the workshop theme. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation.

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IMPORTANT DATES
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Abstract Submission: August 9, 2024 (AoE)  (EXTENDED)
Position or Regular Paper Submission: August 9, 2024 (AoE)  (EXTENDED)
Notification: September 8, 2024
Camera-ready: September 30, 2024
Workshop: November 18, 2024

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SUBMISSIONS
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Submission site: https://urldefense.us/v3/__https://submissions.supercomputing.org/?page=Submit&id=SCWorkshopIA3Abstract&site=sc24__;!!G_uCfscf7eWS!YsDcAIOZQq8GY6M8ex0MDkR0K-m30wKpPlAhjDutsWzoCqJ3fJjGJM7lPCAG3_FP4xsJ1Q3BYr4gvvCDObWfb5eK2Pn2afe7gw$ 

Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four (4) pages for position papers (excluding references).
Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix.

The templates are available at: 
https://urldefense.us/v3/__http://www.ieee.org/conferences_events/conferences/publishing/templates.html__;!!G_uCfscf7eWS!YsDcAIOZQq8GY6M8ex0MDkR0K-m30wKpPlAhjDutsWzoCqJ3fJjGJM7lPCAG3_FP4xsJ1Q3BYr4gvvCDObWfb5eK2PmwZp_NIg$ 

The proceedings of the workshop will be published in the IEEE Digital Library in cooperation with IEEE Computer Society.

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GENERAL CO-CHAIRS
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Antonino Tumeo, PNNL, antonino.tumeo at pnnl.gov
John Feo, PNNL, john.feo at pnnl.gov

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TECHINICAL PROGRAM CO-CHAIRS
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Michela Becchi, North Carolina State University, mbecchi at ncsu.edu
Ana Lucia Verbanescu, University of Twente, a.l.varbanescu at utwente.nl

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SPECIAL TOPIC CO-CHAIRS
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Vito Giovanni Castellana, PNNL, vitogiovanni.castellana at pnnl.gov
Sriram Srinivasan, University of Oregon

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ARTIFACT EVALUATION CHAIR
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Biagio Cosenza, University of Salerno, bcosenza at unisa.it

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INCLUSIVITY CO-CHAIRS
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Sanjukta Bhowmick, PNNL, sanjukta.bhowmick at unt.edu
Marco Minutoli, PNNL, marco.minutoli at pnnl.gov

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TECHNICAL PROGRAM COMMITTEE
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Jason Bakos, University of South Carolina, US
Prerna Budhkar, Intel, US
Martin Burtscher, Texas State University, US
Anastasiia Butko, Lawrence Berkeley National Laboratory, US
Tiziano De Matteis, VU Amsterdam, NL
Reza Farahani, University of Klagenfurt, AT
Holger Froening, Heidelberg University, DE
Oded Green, NVIDIA, US
Giulia Guidi, Cornell University, US
Johannes Langguth, Simula Research Laboratory, NO
John Leidel, Tactical Computing Labs, US
Jiajia Li, North Carolina State University, US
Dong Li, University of California Merced, US
José Moreira, IBM TJ Wattson, US
Maxim Naumov, Meta, US
Fanny Nina Paravecino, Microsoft, US
Gal Oren, Technion, Israel Institute of Technology, IL
Roger Pearce, Lawrence Livermore National Laboratory, US
Joshua Randall, ARM, US
Bradley Rees, NVIDIA, US
Alejandro Rico, AMD, US
Matei Ripeanu, University of British Columbia, CA
Jože Rožanec, Jozef Stefan Institute, SI
Sudip Seal, Oak Ridge National Laboratory, US
John Shalf, Lawrence Berkeley National Laboratory, US
Tyler Sorensen, University of California Santa Cruz, US
Toyotaro Suzumura, University of Tokyo, JP Ruud van der Pas, Oracle, NL
Gwendolyn Voskuilen, Sandia National Laboratories, US
Yuke Wang, University of California, Santa Barbara, US Hancheng Wu, MathWorks, US
Nick Yakovets, Eindhoven University of Technology, NL
Xiaodong Yu, Stevens Institute of Technology, US

Other members TBD