[hpc-announce] Updated CFP: MEMO 24 at SC: International Workshop on Memory System, Management and Optimization - Papers due July 25

[Kyle Hale]

MEMO 24: International Workshop on Memory System, Management and
Optimization will be held in conjunction with SC 24 in Atlanta, GA.

Sunday, November 17, 2024 (2:00PM - 5:30PM) @ the Georgia World Congress
Center, Atlanta

https://urldefense.us/v3/__https://kth-scalab.github.io/events/memo24__;!!G_uCfscf7eWS!Z0FvzlceubxbQAAr2FCvuLp0zxZJt16n6M3Kxne0qRVh0aRLytBHfSUwkKGIFeCqWspC9bhWtBjwm3Vzxaf0rA$ 


The growing disparity between computing speed and memory speed, commonly
referred to as the memory wall problem, remains a critical and enduring
challenge in the computing community. Recent developments, such as the
expansion of the memory hierarchy and the increasingly blurred line between
memory and storage, coupled with the introduction of new memory
technologies, such as high-bandwidth memory, non-volatile memory, and
disaggregated memory, further complicate the situation. The prevalence of
heterogeneous computing, ongoing advancements in the memory hierarchy, and
the rise of disaggregated architectures significantly broaden the scope of
this challenge. Simultaneously, the proliferation of large machine learning
(ML) models, graph processing applications, and traditional scientific
applications facing bottlenecks due to memory latency, bandwidth, or
capacity issues continue to drive researchers, professionals, and
practitioners to enhance memory system design and memory management,
overcome the constraints imposed by the memory wall, and facilitate
high-performance memory-intensive applications.

Computer architecture, operating systems, storage systems, performance
models, tools, and applications themselves are being enhanced or even
redesigned to address the performance, programmability, and energy
efficiency challenges of the increasingly complex and heterogeneous memory
systems. Exploring the intersection of these research areas will enable
cohesive and synergistic development and collaboration on the future of
memory technologies, systems, and applications. Computer architecture and
hardware systems, operating systems, storage and file systems, programming
stack, performance models and tools are being enhanced, augmented, or even
redesigned to address the performance, programmability, and energy
efficiency challenges of the increasingly complex and heterogeneous memory
systems for HPC and data-intensive applications.

WORKSHOP TOPICS

This workshop aims to bring together computer science and computational
science researchers, from industry, government labs and academia, concerned
with the challenges of efficiently using existing and emerging memory
systems. The term performance for memory systems is general, which includes
latency, bandwidth, power consumption and reliability from the aspect of
hardware memory technologies to how it is manifested in the application
performance. The topics of interest include, but are not limited to:

* Evaluation, characterization, performance analysis, and use cases of
emerging memory technologies, including non-volatile memories,
high-bandwidth memory, heterogeneous memory, disaggregated memory, etc.

* Software, hardware, and co-design approaches that ease the adoption and
optimize the use of processing-in-memory and near-memory computing
technologies.

* Programming interfaces or language extensions that improve the
programmability of using emerging memory technologies and systems,
heterogeneous memory system and multi-dimensional data, and unified memory
systems.

* Compiler, runtime, and system techniques for optimizing data layout and
placement, page migration, coherence and consistency enforcement, latency
hiding and improving bandwidth utilization and energy consumption of
heterogeneous memory systems.

* Enhancement or new development for operating systems, storage and file
systems, and I/O system that address challenges of existing and emerging
memory technologies, heterogeneous memory systems, and the blurred boundary
between memory and storage.

* Tools, modeling, evaluation, and case study of memory system behavior and
application performance that reveals the limitations and characteristics of
existing memory systems.

* Application development and optimization for new memory architecture and
technologies and those overcome memory related challenges in their problems.


IMPORTANT DATES
* Full paper submission deadline: July 25, 2024 (AoE)
* Author notification: August 25, 2024 (AoE)
* Camera-ready deadline: September 15, 2024 (AoE)

For full workshop details, see
https://urldefense.us/v3/__https://kth-scalab.github.io/events/memo24__;!!G_uCfscf7eWS!Z0FvzlceubxbQAAr2FCvuLp0zxZJt16n6M3Kxne0qRVh0aRLytBHfSUwkKGIFeCqWspC9bhWtBjwm3Vzxaf0rA$ 

ORGANIZING COMMITTEE
- Ron Brightwell (Sandia National Laboratories, USA)
- Ivy Peng (KTH Royal Institute of Technology, Sweden)
- Kyle Hale (Illinois Institute of Technology, USA)
- Maya Gokhale (Lawrence Livermore National Laboratory, USA)

PROGRAM COMMITTEE
- Jeff Vetter (Oak Ridge National Laboratory, USA)
- Jason Lowe-Power (University of California, Davis; Lawrence Berkeley
National Laboratory, USA)
- Thaleia Dimitra Doudali (IMDEA Software Institute, Spain)
- Seyong Lee (Oak Ridge National Laboratory, USA)
- Gwendolyn Voskuilen (Sandia National Laboratory, USA)
- Jie Ren (College of William & Mary, USA)
- Petar Radojkovic (Barcelona Supercomputing Center (BSC); Polytechnic
University of Catalonia, Spain)
- Shirley Moore (University of Texas, El Paso, USA)
- Christian Pinto (IBM, Ireland)

-- 
Kyle C. Hale, Ph.D.
Associate Professor
Department of Computer Science
Illinois Institute of Technology
10 West 31st Street
Chicago, IL 60616
*https://urldefense.us/v3/__https://halek.co__;!!G_uCfscf7eWS!Z0FvzlceubxbQAAr2FCvuLp0zxZJt16n6M3Kxne0qRVh0aRLytBHfSUwkKGIFeCqWspC9bhWtBjwm3Vmuj1RpQ$  <https://urldefense.us/v3/__http://halek.co/__;!!G_uCfscf7eWS!Z0FvzlceubxbQAAr2FCvuLp0zxZJt16n6M3Kxne0qRVh0aRLytBHfSUwkKGIFeCqWspC9bhWtBjwm3XUpxX99w$ >*