[hpc-announce] [RAW 2024] Reconfigurable Architectures Workshop CFP Round Two Ext'd to Feb 9

Mon Feb 5 14:54:47 CST 2024

       RAW 2024 CALL FOR PAPERS, Extended to Feb 9
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      31st Reconfigurable Architectures Workshop (RAW 2024)
              May 27-28, 2024. San Francisco, CA, USA
                       Website: http://raw.necst.it/
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IMPORTANT DATES:
* Round two submission deadline: extended to Feb 9, 2024
* Round two decision notification: Mar 15, 2024
* Round two camera-ready: Mar 29, 2024
* Conference: May 27-28, 202
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IMPORTANT NOTE:
The two submission rounds are strictly independent chances for submission.
Not having submitted for the first round does not prevent a second round
submission.
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SUBMISSION WEBSITE:
https://ssl.linklings.net/conferences/ipdps/?page=Submit&id=WorkshopRAW2024Round2FullSubmission&site=ipdps2024
(Please choose “Workshop: RAW 2024 Round 2”)
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https://www.facebook.com/groups/ReconfigurableArchitecturesWorkshop/
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The 31st Reconfigurable Architectures Workshop (RAW 2024) will be held in
San Francisco, CA, USA in May 2024. RAW 2024 is associated with the 38th
Annual IEEE International Parallel & Distributed Processing Symposium (IEEE
IPDPS 2024) and is sponsored by the IEEE Computer Society and the Technical
Committee on Parallel Processing. The workshop is one of the major meetings
for researchers to present ideas, results, and on-going research on both
theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of
underlying hardware architectures or devices to rapidly alter (often on the
fly) the functionalities of their components and the interconnection
between them to suit the problem at hand. The area has a rich theoretical
tradition and wide practical applicability. There are several commercially
available reconfigurable platforms (FPGAs and coarse-grained devices) and
many modern applications (including embedded systems and HPC) use
reconfigurable subsystems. An appropriate mix of theoretical foundations
and practical considerations, including algorithms, applications,
architectures, technologies, systems, programming models and tools, is
essential to fully exploit the possibilities offered by reconfigurable
computing. The Reconfigurable Architectures Workshop aims to provide a
forum for creative and productive interaction for researchers and
practitioners in the area.

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NEW for RAW 2024

For RAW 2024, to encourage more submissions and more attendance, we have
two rounds of submissions. Round two submission deadline is extended to Feb
9, 2024. All submission deadlines are with respect to 11:59 pm Anywhere on
Earth (UTC -12).

For RAW 2024, we are collaborating with ACM TRETS to organize a journal
special issue. We will invite top papers from the RAW 2024 program to
extend their work and submit to the ACM TRETS special issue on RAW 2024.
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TOPICS OF INTEREST

Submissions are solicited on the following topics including, but not
limited to:

Applications of Reconfigurable Architectures
* ML/AI Acceleration
* Big Data Analytics Acceleration
* Applications in FinTech
* Applications in Organic Computing, Biologically-Inspired Solutions
* Applications in Computational Genomics and Healthcare
* Applications in Autonomous Driving
* Applications in Digital Media and Entertainment
* Applications in HPC and Datacenters
* Applications in Edge Devices and IoT Devices
* Other Novel Use of Commercial FPGAs

Reconfigurable System Architectures & CAD Support
* Domain-Specific Architectures and Overlays
* Coarse-Grained Reconfigurable Architectures
* Specialized Memory Systems including Volatile, Non-Volatile, and Hybrid
Memory Subsystems
* Near Data Reconfigurable Architectures and Systems (e.g., SmartNIC,
SmartSSD)
* Reconfigurable Datacenters and Cloud
* FPGA-based MPSoC Architectures and Systems
* Emerging Technologies (e.g., Optical Models, 3D Interconnects, Devices)
* Other Evolvable, Adaptable, or Autonomous Reconfigurable Computing Systems
* Low-Level CAD Support for the above Architectures and Systems
* Critical Issues (Security, Reliability, Fault-Tolerance)

Software Programmability and Tool Support
* Domain-Specific Languages and Compilers
* High-Level Synthesis
* System-Level Synthesis
* Runtime Systems
* Operating Systems and Virtualization
* Debugging and Verification Tools
* Runtime Reconfiguration Models
* Partial Reconfiguration Techniques
* Fast Simulation, Prototyping, and Profiling Tools
* Other Tool Support to Facilitate Software-Defined Reconfigurable Computing

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SUBMISSION OF PAPERS

All manuscripts will be reviewed by at least three members of the program
committee, with a single-blind review process. Submissions should be a
complete manuscript or, in special cases, may be a summary of relevant
work. There are two types of manuscripts: 1) full papers (up to 6 pages)
and 2) short papers (up to 4 pages). Both manuscripts should follow the
IEEE conference style: single-spaced, double-column pages using 10-point
size font on 8.5X11 inch pages. The page limits exclude references and both
manuscripts can include up to 2 pages of references. A conformant LaTeX
template is available here:
https://www.ieee.org/content/dam/ieee-org/ieee/web/org/pubs/conference-latex-template_10-17-19.zip.
Overleaf users can find the LaTeX template here:
https://www.overleaf.com/latex/templates/ieee-bare-demo-template-for-conferences/ypypvwjmvtdf.
A Microsoft Word template is available here:
https://www.ieee.org/content/dam/ieee-org/ieee/web/org/conferences/conference-template-letter.docx
.

Papers are to be submitted through Linklings:
https://ssl.linklings.net/conferences/ipdps/?page=Submit&id=WorkshopRAW2024Round2FullSubmission&site=ipdps2024
(Please choose “Workshop: RAW 2024 Round 2”). All papers must be submitted
electronically in PDF format. Submitted papers should not have appeared in
or be under submission for a different workshop, conference or journal. It
is also expected that all accepted papers (full or short) will be presented
at the workshop by one of the authors.

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PUBLICATION AND JOURNAL SPECIAL ISSUE

IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a
printed volume. Proceedings of the workshops are distributed at the
conference and are submitted for inclusion in the IEEE Xplore Digital
Library after the conference. We will also invite top papers from the
workshop to extend their work and submit to the ACM TRETS special issue on
RAW 2024.

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AWARDS

RAW 2024 will have 3 different awards:
* Best paper (selected after the presentation of the 3 best paper
candidates)
* Best poster (selected among all the poster presentations at RAW 2024)
* Best artifact (see the following section for more information)

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ARTIFACT EVALUATION

RAW 2024 will continue the experimental Artifact Evaluation (AE) initiated
in RAW 2023.
Authors of accepted papers at RAW 2024 can optionally participate in the AE
process to formally describe supporting materials(code, data, models,
workflows, results).

Artifacts are digital objects that were created by the authors as part of
the research or experiments performed with the submitted work.  Examples of
artifacts are:
* Software: models, source code, scripts, Makefiles, container images (like
Docker files), etc.
* Hardware: Verilog, VHDL, schematics, CAD tools, flows, etc.
* Data: spreadsheets, databases, binary files, design sets, etc.

High-quality artifacts are as important as the manuscript itself. The goal
of submitting artifacts promotes the availability and reproducibility of
the experimental results and data such that other researchers can repeat
experiments and replicate results with less effort.

Note that this submission is voluntary and will not influence the final
decision regarding the papers. The goal is to help the authors validate
experimental results from their accepted papers by an independent AE
Committee (AEC) in a collaborative way while helping readers find articles
with available (i.e., publicly accessible in an archival repository),
functional (i.e., consistent, documented, and reusable), and validated
(i.e., main results from the paper) artifacts.

Each submitted artifact is evaluated by at least two members of the AEC.
During the process, authors and evaluators are allowed to communicate
anonymously with each other to overcome technical difficulties. Ideally, we
hope to see all submitted artifacts successfully pass the artifact
evaluation. More details on the AE process will follow.

Finally, we are seeking volunteers to take part in the AE Committee. If you
are interested in taking part of this initiative please check the RAW
website at https://raw.necst.it/

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ORGANIZERS

Workshop Chair
Marco Domenico Santambrogio, Politecnico di MIlano, Italy

Program Chair
Zhenman Fang, Simon Fraser University, Canada

Steering Committee
Juergen Becker, Karlsruhe Institute of Technology, Germany
Viktor K. Prasanna, University of Southern California, USA
Ramachandran Vaidyanathan, Louisiana State University, USA
Marco D. Santambrogio, Politecnico di Milano, Italy

Steering Chair
Viktor K. Prasanna, University of Southern California, USA

Artifacts Chair
Davide Conficconi, Politecnico di Milano, Italy

Finance Chair
Andrew Schmidt, AMD, USA

PhD Forum Chair
Peipei Zhou, University of Pittsburgh, USA

Publicity Co-Chairs
Brian Veale, IBM, USA
Christian Pilato, Politecnico di Milano, Italy

Webmaster
Francesco Peverelli, Politecnico di Milano, Italy