[hpc-announce] RAW 2025 CALL FOR PAPERS

Mon Dec 9 14:22:21 CST 2024

RAW 2025 CALL FOR PAPERS
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 32nd Reconfigurable Architectures Workshop (RAW 2025)
         June 3-4, 2025.  Milan, Italy
         Website: https://urldefense.us/v3/__http://raw.necst.it/__;!!G_uCfscf7eWS!Y5KtBtgs5doESbXb-ghAcP0koIWqCFsuBuy0LgKSUbQXLwWBuDdsqZR--0Upxd3F6AbbxckR_b2us59CjQ$ 
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IMPORTANT DATES:
* Submission deadline: Jan 20, 2025
* Decision notification: Feb 14, 2025
* Camera-ready: Mar 6, 2025
* Conference: June 3-4, 2025

All submission deadlines are 11:59 pm Anywhere on Earth (UTC -12).
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SUBMISSION WEBSITE:
https://urldefense.us/v3/__https://ssl.linklings.net/conferences/ipdps/?page=Submit&id=WorkshopRAW2025FullSubmission&site=ipdps2025__;!!G_uCfscf7eWS!Y5KtBtgs5doESbXb-ghAcP0koIWqCFsuBuy0LgKSUbQXLwWBuDdsqZR--0Upxd3F6AbbxckR_b2Ba3hgRg$ 
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FOLLOW US ON FACEBOOK
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The 32nd Reconfigurable Architectures Workshop (RAW 2025) will be held in
Milan, Italy in June 2025. RAW 2025 is associated with the 39th Annual IEEE
International Parallel & Distributed Processing Symposium (IEEE IPDPS 2025)
and is sponsored by the IEEE Computer Society and the Technical Committee
on Parallel Processing. The workshop is one of the major meetings for
researchers to present ideas, results, and on-going research on both
theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of
underlying hardware architectures or devices to rapidly alter (often on the
fly) the functionalities of their components and the interconnection
between them to suit the problem at hand. The area has a rich theoretical
tradition and wide practical applicability. There are several commercially
available reconfigurable platforms (FPGAs and coarse-grained devices) and
many modern applications (including embedded systems and HPC) use
reconfigurable subsystems. An appropriate mix of theoretical foundations
and practical considerations, including algorithms, applications,
architectures, technologies, systems, programming models and tools, is
essential to fully exploit the possibilities offered by reconfigurable
computing. The Reconfigurable Architectures Workshop aims to provide a
forum for creative and productive interaction for researchers and
practitioners in the area.

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TRETS special issue on RAW 2025

After the experiments of RAW2024, we will continue to push for a journal
special issue.
For RAW 2025, we are collaborating with ACM TRETS to organize a journal
special issue. We will invite top papers from the RAW 2025 program to
extend their work and submit to the ACM TRETS special issue on RAW 2025.
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TOPICS OF INTEREST

Submissions are solicited on the following topics including, but not
limited to:

Applications of Reconfigurable Architectures
* ML/AI Acceleration
* Big Data Analytics Acceleration
* Applications in FinTech
* Applications in Organic Computing, Bio-Inspired Solutions, and
Neuromorphic Computing
* Applications in Computational Genomics, Healthcare, and Biomedical Vision
* Applications in Autonomous Driving
* Applications in Digital Media and Entertainment
* Applications in HPC and Datacenters
* Applications in Edge Devices and IoT Devices
* Applications in Cybersecurity
* Other Novel Use of Commercial FPGAs

Reconfigurable System Architectures & CAD Support
* Domain-Specific Architectures and Overlays
* Coarse-Grained Reconfigurable Architectures
* Specialized Memory Systems including Volatile, Non-Volatile, and Hybrid
Memory Subsystems
* Near Data Reconfigurable Architectures and Systems (e.g., SmartNIC,
SmartSSD)
* Reconfigurable Datacenters and Cloud
* FPGA-based MPSoC Architectures and Systems
* Heterogeneous Systems
* Emerging Technologies (e.g., Quantum, Optical Models, 3D Interconnects,
Devices)
* Other Evolvable, Adaptable, or Autonomous Reconfigurable Computing Systems
* Low-Level CAD Support for the above Architectures and Systems
* Critical Issues (Security, Reliability, Fault-Tolerance)

Software Programmability and Tool Support
* Domain-Specific Languages and Compilers
* High-Level Synthesis
* System-Level Synthesis
* Runtime Systems
* Operating Systems and Virtualization
* Debugging and Verification Tools
* Runtime Reconfiguration Models
* Partial Reconfiguration Techniques
* Fast Simulation, Prototyping, and Profiling Tools
* Other Tool Support to Facilitate Software-Defined Reconfigurable Computing

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SUBMISSION OF PAPERS

All manuscripts will be reviewed by at least three members of the program
committee, with a single-blind review process. Submissions should be a
complete manuscript or, in special cases, may be a summary of relevant
work. There are two types of manuscripts: 1) full papers (up to 6 pages)
and 2) short papers (up to 4 pages). Both manuscripts should follow the
IEEE conference style: single-spaced, double-column pages using 10-point
size font on 8.5X11 inch pages. The page limits exclude references and both
manuscripts can include up to 2 pages of references. A conformant LaTeX
template is available here:
https://urldefense.us/v3/__https://www.ieee.org/content/dam/ieee-org/ieee/web/org/pubs/conference-latex-template_10-17-19.zip__;!!G_uCfscf7eWS!Y5KtBtgs5doESbXb-ghAcP0koIWqCFsuBuy0LgKSUbQXLwWBuDdsqZR--0Upxd3F6AbbxckR_b0fn7bsJA$ .
Overleaf users can find the LaTeX template here:
https://urldefense.us/v3/__https://www.overleaf.com/latex/templates/ieee-bare-demo-template-for-conferences/ypypvwjmvtdf__;!!G_uCfscf7eWS!Y5KtBtgs5doESbXb-ghAcP0koIWqCFsuBuy0LgKSUbQXLwWBuDdsqZR--0Upxd3F6AbbxckR_b1rMWv9RQ$ .
A Microsoft Word template is available here:
https://urldefense.us/v3/__https://www.ieee.org/content/dam/ieee-org/ieee/web/org/conferences/conference-template-letter.docx__;!!G_uCfscf7eWS!Y5KtBtgs5doESbXb-ghAcP0koIWqCFsuBuy0LgKSUbQXLwWBuDdsqZR--0Upxd3F6AbbxckR_b0GsC6FhA$ 
.

Papers are to be submitted through Linklings:
https://urldefense.us/v3/__https://ssl.linklings.net/conferences/ipdps/?page=Submit&id=WorkshopRAW2025FullSubmission&site=ipdps2025__;!!G_uCfscf7eWS!Y5KtBtgs5doESbXb-ghAcP0koIWqCFsuBuy0LgKSUbQXLwWBuDdsqZR--0Upxd3F6AbbxckR_b2Ba3hgRg$ .
All papers must be submitted electronically in PDF format. Submitted papers
should not have appeared in or be under submission for a different
workshop, conference or journal. It is also expected that all accepted
papers (full or short) will be presented at the workshop by one of the
authors.
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PUBLICATION AND JOURNAL SPECIAL ISSUE

IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a
printed volume. Proceedings of the workshops are distributed at the
conference and are submitted for inclusion in the IEEE Xplore Digital
Library after the conference. We will also invite top papers from the
workshop to extend their work and submit to the ACM TRETS special issue on
RAW 2025.

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AWARDS

RAW 2025 will have 3 different awards:
* Best paper (selected after the presentation of the 3 best paper
candidates)
* Best poster (selected among all the poster presentations at RAW 2025)
* Best artifact (see the following section for more information)

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CALL FOR PH.D. FORUM

The Reconfigurable Architectures Workshop (RAW) is pleased to announce the
Ph.D Forum. The forum is an excellent opportunity for PhD students to
present their research and engage with the broader reconfigurable computing
community. PhD students conducting research in reconfigurable computing and
related fields are invited to participate in the poster session, where they
can share their work, exchange ideas, and receive feedback from experienced
researchers and peers. To apply for the forum, prospective participants
will be required to submit a two-page extended abstract.
More details will be communicated around February.

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ARTIFACT EVALUATION

RAW 2025 will continue the experimental Artifact Evaluation (AE) initiated
in RAW 2023.
Authors of accepted papers at RAW 2025 can optionally participate in the AE
process to formally describe supporting materials(code, data, models,
workflows, results).

Artifacts are digital objects that were created by the authors as part of
the research or experiments performed with the submitted work.  Examples of
artifacts are:
* Software: models, source code, scripts, Makefiles, container images (like
Docker files), etc.
* Hardware: Verilog, VHDL, schematics, CAD tools, flows, etc.
* Data: spreadsheets, databases, binary files, design sets, etc.

High-quality artifacts are as important as the manuscript itself. The goal
of submitting artifacts promotes the availability and reproducibility of
the experimental results and data such that other researchers can repeat
experiments and replicate results with less effort.

Note that this submission is voluntary and will not influence the final
decision regarding the papers. The goal is to help the authors validate
experimental results from their accepted papers by an independent AE
Committee (AEC) in a collaborative way while helping readers find articles
with available (i.e., publicly accessible in an archival repository),
functional (i.e., consistent, documented, and reusable), and validated
(i.e., main results from the paper) artifacts.

Each submitted artifact is evaluated by at least two members of the AEC.
During the process, authors and evaluators are allowed to communicate
anonymously with each other to overcome technical difficulties. Ideally, we
hope to see all submitted artifacts successfully pass the artifact
evaluation. More details on the AE process will follow, and in the meantime
check the FAQ

Finally, we are seeking volunteers to take part in the AE Committee. If you
are interested in taking part in this initiative please consider to submit
your candidacy or those of your students through this form:
https://urldefense.us/v3/__https://forms.gle/5de1vCC5yomMQ3B39__;!!G_uCfscf7eWS!Y5KtBtgs5doESbXb-ghAcP0koIWqCFsuBuy0LgKSUbQXLwWBuDdsqZR--0Upxd3F6AbbxckR_b3PRCjBfQ$ 
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ORGANIZERS

Workshop Chair
Marco Domenico Santambrogio, Politecnico di MIlano, Italy

Program Chair
Davide Conficconi, Politecnico di Milano, Italy
Zhenman Fang, Simon Fraser University, Canada

Steering Committee
Juergen Becker, Karlsruhe Institute of Technology, Germany
Viktor K. Prasanna, University of Southern California, USA
Ramachandran Vaidyanathan, Louisiana State University, USA
Marco D. Santambrogio, Politecnico di Milano, Italy

Steering Chair
Viktor K. Prasanna, University of Southern California, USA

Artifact Evaluation Chair
Francesco Peverelli, Politecnico di Milano, Italy

PhD Forum Chair
Antonio Miele, Politecnico di Milano, Italy

Publicity Co-Chairs
Brian Veale, IBM, USA
Christian Pilato, Politecnico di Milano, Italy

Webmaster
Laura Ginestretti, Politecnico di Milano, Italy