[hpc-announce] [ICCD'23] Call for Participation; Early Registration Deadline Monday in One Week
Lars Bauer
lars.bauer at kit.edu
Sun Oct 8 12:35:03 CDT 2023
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Call for Participation
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2023 IEEE International Conference on Computer Design (ICCD)
Nov 6-8, 2023
Washington DC, USA
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Webpage: https://www.iccd-conf.com/
ICCD encompasses a wide range of topics in the research, design,
and implementation of computer systems and their components.
ICCD’s multi-disciplinary emphasis provides an ideal environment
for developers and researchers to discuss practical and theoreti-
cal work covering systems and applications, computer architecture,
verification and test, design tools and methodologies, circuit
design, and technology.
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NEWS
* Registration link is live
https://www.iccd-conf.com/Conference_Registration.html
* Final Program is live
https://www.iccd-conf.com/agenda.html
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IMPORTANT DATES:
Oct. 16 Early Registration Deadline
Nov. 6-8 ICCD in Washington DC, USA
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KEYNOTES: https://www.iccd-conf.com/keynote.html
* Azalia Mirhoseini, Anthropic and Stanford University, "Pushing
the Limits of Scaling Laws in the Age of Large Language Models"
* David Atienza, Ecole polytechnique federale de Lausanne (EPFL),
"Accelerator-Based Edge AI Architectures for a Connected and
Sustainable World"
* David Z. Pan, UT Austin, "AI for Chip Design & EDA:
Everything, Everywhere, All at Once (?)"
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AGENDA OVERVIEW: https://www.iccd-conf.com/agenda.html
Monday, Nov. 6th
* Keynote: Azalia Mirhoseini (Anthropic and Stanford University) -
Pushing the Limits of Scaling Laws in the Age of Large Language
Models
* Sessions on: Verification & Security, Logic and Circuit Design,
Brain-Inspired Circuits, Quantum Computing, SRAM & NVM, Cache
Memory, Accelerators, Persistent Memory, Storage, Memory Systems
Tuesday, Nov. 7th
* Keynote: David Atienza (EPFL) - Accelerator-Based Edge AI
Architectures for a Connected and Sustainable World
* Panel: Technologies, Systems, and Techniques to support Novel
Computing Paradigms
* Sessions on: GPU & Graph, File Systems, SSDs, Logic Synthesis,
GPU, Accelerators, Co-Design, Dataflow & Reinforcement Learning
Wednesday, Nov. 8th
* Keynote: David Z. Pan (UT Austin) - AI for Chip Design & EDA:
Everything, Everywhere, All at Once (?)
* Sessions on: Matrix Multiplication & Sparsity, Fault Tolerance &
Resilience, Test & Verification, Compression & Accelerators,
Processing-In-Memory, Electronic Design Automation
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Organizing Committee: https://www.iccd-conf.com/Organizing_Committee.html
General Chairs: Guru Prasadh Venkataramani, George Washington University, USA
Rathish Jayabharathi, Intel, USA
Program Chairs: Christian Pilato, Politecnico di Milano, Italy
Pedro Trancoso, Chalmers University of Technology, Sweden
Steering Committee:
Georgi Gaydadjiev, TU Delft, Netherlands
Kee Sup Kim, Synopsys, USA
Omer Khan, University of Connecticut, USA
Peter-Michael Seidel, University of Hawaii, USA
Sandip Kundu, University of Massachusetts Amherst, USA
Sponsored by the IEEE Computer Society
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