[hpc-announce] [ICCD'23] CfP: 1 Week Deadline Extension: June 23, 2023

Lars Bauer lars.bauer at kit.edu
Fri Jun 9 03:41:48 CDT 2023

                          Call for Papers
     2023 IEEE International Conference on Computer Design (ICCD)
                           Nov 6-8, 2023
                        Washington DC, USA
      June 23  Abstract submission (extended)
      June 23  Full paper submission (extended)
      Aug 25   Notification of acceptance
Webpage: https://www.iccd-conf.com/

ICCD encompasses a wide range of topics in the research, design,
and implementation of computer systems and their components.
ICCD’s multi-disciplinary emphasis provides an ideal environment
for developers and researchers to discuss practical and theoreti-
cal work covering systems and applications, computer architecture,
verification and test, design tools and methodologies, circuit
design, and technology.

We especially encourage submissions that look forward to
future systems and technologies. Authors are asked to submit
technical papers in accordance to the submission guidelines
in one of the following tracks:

Track 1. Computer Systems:
System architecture and software (compiler, programming language/
model, firmware, OS, hypervisor, runtime) design and co-design for
embedded/real-time systems; System support and compilers for
multi/many cores, co-processors, and accelerators; System support
for security, reliability, and energy efficiency and proportionality;
Virtual memory; System support for emerging technologies, including
NVM, quantum, neuromorphic, bio-inspired computing, machine learning
and artificial intelligence applications; Specialized OS, runtime,
and storage systems for data center and cloud/edge computing, high-
performance computing (HPC), exascale system, and serverless computing.

Track 2. Processor Architecture:
Microarchitecture design techniques for single-threaded and multi/
many-core processors, such as instruction-level parallelism,
pipelining, caches, branch prediction, multithreading, and networks-
on-chip; Techniques for low-power, secure, and reliable processor
architectures; Hardware acceleration for emerging applications
including NVM, quantum, neuromorphic, bio-inspired; Hardware support
for processor virtualization; Real-life design challenges: case
studies, tradeoffs, retrospectives.

Track 3. Test, Verification, and Security:
Design error debug and diagnosis; Fault modeling; Fault simulation
and ATPG; Analog/RF testing; Statistical test methods; Large volume
yield analysis and learning; Fault tolerance; DFT and BIST;
Functional, transaction-level, RTL, and gate-level modeling and
verification of hardware designs; Equivalence checking, property
checking, and theorem proving; Constrained-random test generation;
High-level design and SoC validation; Hardware security primitives
and methodologies; Side-channel analysis, attacks and mitigations
for processors and accelerators; Interaction between test, security
and trust.

Track 4. Electronic Design Automation:
System-level design and synthesis; High-level, logic and physical
synthesis; Analysis and optimization of timing, power, variability/
yield, temperature, and noise; Physical design, including
partitioning, floorplanning, placement, and routing; Clocktree
synthesis; Verification methods at different levels of the EDA flow;
Tools for multiple-clock domains, asynchronous, and mixed-timing
methodologies; CAD support for accelerators, FPGAs, SoCs, ASICs, NoC,
and general-purpose processors; CAD for manufacturing, test,
verification, and security; Tools and design methods for emerging
technologies (photonics, MEMS, spintronics, nano, quantum);
interaction of EDA and AI/ML.

Track 5. Logic and Circuit Design:
Circuit design techniques for digital, memory, analog and mixed-
signal systems; Circuit design techniques for high performance
and low power; Circuit design techniques for robustness under
process variability, electromigration, and radiation; Design
techniques for emerging and maturing technologies (MEMS, nano-
spintronics, quantum, flexible electronics, multi-gate devices,
in-memory computing); Asynchronous circuit design; Signalprocessing,
graphic-processor, and datapath circuits.

A complete version of the paper should be submitted
as a PDF file following the submission guidelines.
Any questions about submission should be directed to
the Program Chairs, Christian Pilato and Pedro Trancoso.
Please consult the ICCD 2023 website for additional
information about the conference and submission details.

General Chairs: Guru Prasadh Venkataramani, George Washington University, USA
                 Rathish Jayabharathi, Intel, USA
Program Chairs: Christian Pilato (Politecnico di Milano)
                 Pedro Trancoso, Chalmers University of Technology, Sweden
Web Chair:      Masab Ahmad, Intel, USA
Steering Committee:
                 Georgi Gaydadjiev, University of Groningen, Netherlands
                 Kee Sup Kim, Synopsys, USA
                 Omer Khan, University of Connecticut, USA
                 Peter-Michael Seidel, University of Hawaii, USA
                 Sandip Kundu, University of Massachusetts Amherst, USA

Sponsored by the IEEE Computer Society

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