[hpc-announce] [CFP] IA^3 2023: 13th SC Workshop on Irregular Applications: Architectures and Algorithms - DEADLINE EXTENDED

[Tumeo, Antonino]

[Please accept our apologies for multiple postings.]

!!!! NEWS: DEADLINE EXTENDED TO AUGUST 7 !!!!

IA^3 2023
13th Workshop on Irregular Applications: Architectures and Algorithms
https://hpc.pnl.gov/IA3/
November 12, 2022
Denver, CO
In conjunction with SC23
In cooperation with ACM

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CALL FOR PAPERS
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Emerging data-intensive, supercomputing applications are moving towards a convergence of scientific simulations, data analytics, and learning algorithms. Many of the components of these applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. In processing massive sets of unstructured data, the components often execute many irregular, fine-grainaccesses and synchronization events. Since current high-performance programming models, runtimes, and architectures rely on regular task graphs, bulk synchronous communications and high temporal and spatial data locality to reduce operational latencies, it is difficult to express irregular applications in current HPC programming models and scale performance on current supercomputing machines. Development of improved programming and execution models that address the issues of irregular applications is critical to solving the data challenges in large-scale science and data analysis.
 This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system architecture, network, languages and libraries, runtimes, compilers, algorithms, and performance studies. Topics of interest, of both theoretical and practical significance, include but are not limited to:
 - Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors 
- Network architectures and interconnects including high-radix and optical networks 
- Novel memory architectures and designs (including processors-in memory) 
- Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing) 
- Modeling, simulation, and evaluation of novel architectures with irregular workloads 
- Languages and programming models for irregular workloads
- Library and runtime support for irregular workloads
- Compiler and analysis techniques for irregular workloads
- Innovative algorithmic techniques for irregular workloads
- Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.)
- Impact of irregularity on machine learning approaches
- Parallelization techniques and data structures for irregular workloads
- Data structures combining regular and irregular computations (e.g., attributed graphs)
- Approaches for managing massive unstructured datasets (including streaming data) 
- High performance data analytics applications (including graph databases and solutions that combine graph algorithms with machine learning)
- Applications that integrate scientific simulation, data analytics, and learning, and require efficient execution of irregular workloads
 The workshop welcomes regular paper submissions, papers describing work-in-progress or incomplete but sound, as well as innovative ideas related to the workshop theme. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation.

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IMPORTANT DATES
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Abstract Submission: August 7, 2023 (AoE) (EXTENDED)
Position or Regular Paper Submission: August 7, 2023 (AoE) (EXTENDED)
Notification: September 8, 2023
Camera-ready: September 29, 2023
Workshop: November 18, 2023

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SUBMISSIONS
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Submission site: https://submissions.supercomputing.org

Submitted manuscripts may not exceed eight (8) pages in length for regular papers (excluding references) and four (4) pages for position papers (including references).
Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix.

The templates are available at: 
https://www.acm.org/publications/proceedings-template
(We are using the old workflows)

The proceedings of the workshop will be published in ACM Digital Library.

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GENERAL CO-CHAIRS
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Antonino Tumeo, PNNL, antonino.tumeo at pnnl.gov
John Feo, PNNL, john.feo at pnnl.gov

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TECHINICAL PROGRAM CO-CHAIRS
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Nesreen Ahmed, Intel, nesreen.k.ahmed at intel.com
Sanjukta Bhowmick, University of North Texas, sanjukta.bhowmick at unt.edu

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ARTIFACT EVALUATION CHAIR
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Biagio Cosenza, University of Salerno, bcosenza at unisa.it

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INCLUSIVITY CO-CHAIRS
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Vito Giovanni Castellana, PNNL, vitogiovanni.castellana at pnnl.gov
Marco Minutoli, PNNL, marco.minutoli at pnnl.govTechnical Program CommitteeJohnathan Alsop, AMD, US 

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TECHNICAL PROGRAM COMMITTEE
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Johnathan Alsop, AMD, US 
Ariful Azad, Indiana University, US
Michela Becchi, North Carolina State University, US 
Prerna Budhkar, Intel, US
Anastasiia Butko, Lawrence Berkeley National Laboratory, US
Eric Cheng, Laboratory of Physical Sciences, US
Daniele De Sensi, Sapienza University of Rome, IT
Oded Green, NVIDIA, US
Giulia Guidi, Cornell University, US
Rajiv Gupta, University of California, San Diego, US 
Ali Jannesari, University of Iowa, US
Peter M. Kogge, Notre Dame University, US 
Manoj Kumar, IBM TJ Watson, US
John Leidel, Tactical Computing Laboratories, US 
Kamesh Madduri, Pennsylvania State University, US
Tim Mattson, Intel, US
José Moreira, IBM TJ Watson, US
Maxim Naumov, Meta, US 
Fanny Nina Paravecino, Microsoft, US 
Gal Oren, Technion, IL
Brian A. Page, Laboratory of Physical Sciences, US
Roger Pearce,  Lawrence Livermore National Laboratory, US
Cynthia Phillips, Sandia National Laboratories, US
Joshua Randall, ARM, US
Bradley Rees, NVIDIA, US
Alejandro Rico, AMD, US
Thomas B. Rolinger, Laboratory of Physical Sciences, US
Nicolas PD Sawaya, Intel, US
Catherine Schuman, University of Tennessee, Knoxville, US
Sudip Seal, Oak Ridge National Laboratory, US 
John Shalf, Lawrence Berkeley National Laboratory, US
Edgar Solomonik, University of Illinois, Urbana Champaign, US
Tyler Sorensen, University of California Santa Cruz, US
Ruud van der Pas, Oracle, NL
Ana Lucia Varbanescu, University of Twente, NL 
Flavio Vella, University of Trento, IT 

Other Members TBD