[hpc-announce] CFP - Workshop on Machine Learning for Software Hardware Co-Design (MLSH)

[Mohamed Riyadh Baghdadi]

                                    Call for Papers
             International Workshop on Machine Learning for
                    Software Hardware Co-Design (MLSH)
                             in Conjunction with PACT
                    http://groups.csail.mit.edu/commit/mlsh/


Important Dates
Paper submission: August 11th (AOE), 2023
Paper notification: August 28th, 2023
Camera-ready: September 25th, 2023
Workshop: October 22nd, 2023

Overview
As Machine Learning (ML) continues to permeate all areas of computing, software system designers and software stack developers are adopting ML solutions and designs to solve challenging problems presented in their areas; especially in areas like optimization and hardware design. ML is increasingly being used to solve a diverse set of problems such as the design of cost models, code optimization heuristics, efficient search space exploration, automatic optimization, and program synthesis. Designing accurate machine learning models, feature engineering, verification, and validation of obtained results and selecting and curating representative training data are all examples of challenging but important problems in this area that are actively being explored by a large community of researchers in industry and academia. This workshop provides a great venue for the international research community to share ideas and techniques to apply machine learning to system challenges with a focus on the software stack and hardware.

Scope
We will solicit papers on topics including, but not limited to, the following areas:
- ML for the software stack
	* Heuristics and cost model construction.
	* Optimization space exploration.
	* Automatic code optimization.
	* Bug detection.
	* Program synthesis.
	* Program and code representation.
	* Important training paradigms.
- ML for hardware
	* ML models for optimal configuration for FPGA.
	* Load balancing between CPU and accelerators (e.g. GPUs, TPUs, etc).
	* ML models to improve computer architecture design.
	* Analysis and techniques to define meaningful representation
(features) for compilers and hardware.
- Training data
	* Exploring the availability or generation of efficient training
data for compilers and hardware.
	* Utilizing graph-based data for machine learning.


Submission Guidelines
We invite both full-length research papers and short research papers. The submitted paper should not exceed the page limit (8 pages for full-length and 4 pages for short papers) and should follow the IEEE conference proceedings templates (https://drive.google.com/uc?export=download&id=1yWTjG2Y8mcSYq1WReEKXT3Z2s6dj0lx ). The page limit applies to all content NOT including references, and there is no page limit for references.

The submission will be reviewed by at least three program committee members and should not have been published in or under review for another venue. Accepted papers will be published in our online proceedings. Submit your paper using this link (https://easychair.org/conferences/?conf=mlsh23).

Program Committee
TBD

Past Editions
MLSH'21: http://groups.csail.mit.edu/commit/mlsh/2021/  
MLSH'20: http://groups.csail.mit.edu/commit/mlsh/2020/  

Organizers
Eun Jung (EJ) Park (Qualcomm Inc).
Riyadh Baghdadi (New York University Abu Dhabi).
Joseph Manzano (Pacific Northwest National Laboratory).
Joshua Suetterlein (Pacific Northwest National Laboratory).