[hpc-announce] [EXTD DEADLINE] 30th Anniversary of RAW CFP: Reconfigurable Architectures Workshop

Brian Veale veale at acm.org
Sun Jan 22 15:41:15 CST 2023

               CALL FOR PAPERS
  30th Reconfigurable Architectures Workshop
                         RAW 2023
   15 May 2023. St. Petersburg, Florida USA

              Web site: http://raw.necst.it/
              Submissions: https://easychair.org/conferences/?conf=raw23
              Submission deadline: February 10, 2023
              Decision notification: March 1, 2023
              Camera-Ready papers due: March 7, 2023

At RAW 2023 will celebrate our 30th anniversary by having 3 different awards:
• Best paper (selected after the presentation of the 3 best paper candidates)
• Best poster (selected among all the short papers presenting also a
poster at RAW2023)
• Best artifacts (see Artifact Evaluation below)

See Awards and Artifact Evaluation below for more information


The 30th Reconfigurable Architectures Workshop (RAW 2023) will be held in
St. Petersburg, Florida USA in May 2023. RAW 2023 is associated with
the 37th Annual
IEEE International Parallel & Distributed Processing Symposium (IEEE
IPDPS 2023) and
is sponsored by the IEEE Computer Society and the Technical Committee
on Parallel
Processing. The workshop is one of the major meetings for researchers to present
ideas, results, and on-going research on both theoretical and
practical advances in
Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability
of underlying
hardware architectures or devices to rapidly alter (often on the fly) the
functionalities of their components and the interconnection between
them to suit the
problem at hand. The area has a rich theoretical tradition and wide practical
applicability. There are several commercially available reconfigurable platforms
(FPGAs and coarse-grained devices) and many modern applications
(including embedded
systems and HPC) use reconfigurable subsystems. An appropriate mix of
foundations and practical considerations, including algorithms architectures,
applications, technologies and tools, is essential to fully exploit
the possibilities
offered by reconfigurable computing. The Reconfigurable Architectures
Workshop aims
to provide a forum for creative and productive interaction for researchers and
practitioners in the area.


All manuscripts will be reviewed by at least three members of the
program committee. Submissions should be a complete manuscript or,
in special cases, may be a summary of relevant work. Manuscript for
full paper should be not exceed 8 single-spaced, double-column pages
using 10-point size font on 8.5X11 inch pages (IEEE conference style)
including references, figures and tables. Manuscript for short papers
should be not exceed 4 single-space, double-column pages.
Papers are to be submitted through EasyChair. Submitted papers should
not have appeared in or be under consideration for a different workshop,
conference or journal. It is also expected that all accepted papers
(regular or short) will be presented at the workshop by one of the

All papers must be submitted electronically in PDF format. Submissions can
be made through:
. the RAW2018 web site: http://raw.necst.it/
. EasyChair: https://easychair.org/conferences/?conf=raw23


              Submission deadline January 23, 2023
              Decision notification February 14, 2023
              Conference: May 15, 2023


At RAW 2023 will celebrate our 30th anniversary by having 3 different
. Best paper (selected after the presentation of the 3 best paper candidates)
. Best poster (selected among all the short papers presenting also a
poster at RAW2023)
. Best artifacts (see the following section for more information)


In 2023 RAW will celebrate the 30th anniversary, by giving authors the
to submit for evaluation artifacts that accompany their research work.
This year this will be a first
experiment in this direction. A paper is more than the document
itself; it is made o a constellation
of artifacts: code, data sets, models, test suites, benchmarks, and
others. High-quality
artifacts are important as the manuscript itself. Indeed they are
needed to reproduce
experimental results and build on top of others' research. Because of
this context, we are opening a
special call for artifacts.

Authors of accepted RAW 2023 papers are invited to formally describe
supporting materials
(code, data, models, workflows, results) to the Artifact Evaluation
(AE) process, and for
any issue, communicate with the Artifacts Chair Davide Conficconi
<davide.conficconi at polimi.it>. Note that this submission is voluntary
and will not
influence the final decision regarding the papers. The goal is to help
the authors validate
experimental results from their accepted papers by an independent AE
Committee in a
collaborative way while helping readers find articles with available
(i.e., publicly
accessible in an archival repository), functional (i.e., consistent,
documented, and
reusable), and validated (i.e., main results from the paper) artifacts!

Each submitted artifact is evaluated by at least two members of the AE
committee. During the process, authors and evaluators are allowed to communicate
anonymously with each other to overcome technical difficulties.
Ideally, we hope to see all
submitted artifacts successfully pass the artifact evaluation.

More details on the AE process will follow.


Hot Topics
    Configurable Cloud
    Heterogeneous Computing in Data Centers
    Accelerating Data Center Workloads
    FPGA-based Deep Learning
    Accelerating Genomic Computations
    Accelerating Data Analytics
    Reconfigurable Computing in the IoT era
    Organic Computing, Biologically-Inspired Solutions
    Applications in Finance

Architectures & CAD
    Algorithmic Techniques and Mapping
    Emerging Technologies (optical models, 3D Interconnects, devices)
    Reconfigurable Accelerators
    Embedded systems and Domain-Specific solutions (Digital Media,
Gaming, Automotive applications)
    FPGA-based MPSoC and Multicore
    Distributed Systems & Networks
    Wireless and Mobile Systems
    Critical issues (Security, Energy efficiency, Fault-Tolerance)

Runtime/System Management
    RunTime Reconfiguration Models
    Autonomic computing systems
    Operating Systems and High-Level Synthesis
    High-Level Design Methods (Hardware/Software co-design, Compilers)
    System Support (Soft processor programming)
    Runtime Support
    Reconfiguration Techniques (reusable artifacts)
    Simulations and Prototyping (performance analysis, verification tools)


Workshop Chair
    Marco D. Santambrogio, Politecnico di Milano, Italy

Program Chair
    Lana Josipović, ETH Zurich, Switzerland

Steering Committee
    Juergen Becker, Karlsruhe Institute of Technology, Germany
    Viktor K. Prasanna, University of Southern California, USA
    Ramachandran Vaidyanathan, Louisiana State University, USA

Steering Chair
    Viktor K. Prasanna, University of Southern California, USA

Artifacts Chair
    Davide Conficconi, Politecnico di Milano, Italy

Publicity Co-Chairs
    Brian Veale, IBM, USA
    Dirk Stroobandt, Ghent University, Belgium
    Yukinori Sato, Toyohashi University of Technology, Japan

    Francesco Peverelli, Politecnico di Milano, Italy

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