[hpc-announce] --:: Deadline Extended (FINAL) ::-- [CFP] The Second International Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing (CGRA4HPC) held in conjunction with IPDPS'23

[Artur Podobas]

The Second International Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing (CGRA4HPC)



 -----------------------  GENERAL INFORMATION -------------------------



CGRA4HPC 2023 will be held in conjunction with IPDPS 2023, St. Petersburg, Florida,  USA



When: Monday the 15th May, 2023

Where: St. Petersburg, Florida, USA



Website: http://cgra4hpc.podobas.net/



Submission Link: https://ssl.linklings.net/conferences/ipdps/?page=Submit&id=CGRA4HPCWorkshopFullSubmission&site=ipdps2023



Important Deadlines

  Paper submission: February 10th, 2023 (EXTENDED, FINAL)

  Paper notification: February 18th, 2023

  Camera-ready due: February 28th, 2023



--------------------------  DESCRIPTION ------------------------------

Coarse-grained reconfigurable arrays (CGRAs) are programmable logic devices that offer plasticity/reconfigurability, albeit at a coarse-grained (word-configurable) level in comparison to fine-grained FPGAs. Such reconfigurability allows the silicon to be specialized towards a particular application in order to reduce data movement and improve performance and energy efficiency. Unlike their cousins, the Field-Programmable Gate Arrays (FPGAs), CGRAs provide reconfigurable Arithmetic Logic Units (ALUs) and a highly specialized yet versatile data path. This ``coarsening'' of reconfiguration allows CGRAs to achieve a significant (custom ASIC-like) reduction in power consumption and increase in operating frequency compared to FPGAs. At the same time, they remedy and overcome the expensive von Neumann (instruction-decoding) overhead that traditional general-purpose processors (CPUs) suffer from. In short, CGRAs strike a seemingly perfect balance between the reconfigurability of FPGAs and the performance of CPUs, with power-consumption characteristics closer to custom ASICs.



The International Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing (CGRA4HPC) aspires to provide a recurring forum for HPC experts and CGRA hardware researchers from academia or industry to come together and discuss state-of-the-art CGRA research for use in emerging HPC systems.



 -----------------------  TOPICS OF INTEREST -------------------------

Topics of interest include (but are not limited to):



 * CGRA Hardware and Architectures

     - Novel high-performance CGRA architectures for use in HPC

     - Energy-efficient architectures (incl. asynchronous/clockless

        CGRAs, power-consumption optimizations, etc.)



 * Hybrid Processor/CGRA Technology

     - Software-programmable CGRAs (e.g., Xilinx ACAP Versal)

     - Processors with a tightly interconnected CGRA subsystem

     - Combination of CGRAs and other emerging post-Moore models (e.g., neuromorphic systems)



  * Programming Models, Compilers, and Middleware

     - Parallel programming language support for programming CGRA

       architectures (e.g., supporting OpenMP or CUDA/HIP for

       programming CGRA architectures)

     - Compilation strategies, algorithms, and methods for mapping

        computations and applications onto modern CGRA architectures

     - Smart middleware and runtime systems for support of CGRAs,

        including multi-CGRA systems for HPC



* Use-Cases and Experiments

     - Experience in porting scientific kernels and applications to

       state-of-the-art CGRAs (e.g., weather/climate codes, CFD, MD,

       etc.)

     - Machine Learning applications and case studies, performance

       and power-efficiency comparisons between traditional systems

       (CPUs/GPUs) and CGRAs



--------------------------  SUBMISSION ------------------------------

We welcome authors to contribute full-length research papers subject to the topics of interest described above. Contributions should be unpublished and not for consideration in other venues. We will adopt a single-blind review process for all papers. Papers should not exceed eight (8) single-spaced pages, formatted in the double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style). Accepted papers will be included in the workshop proceedings, that will be distributed at the conference and are submitted for inclusion in the IEEE Xplore Digital Library after the conference.



We also welcome presentations on new and emerging CGRA technologies from industry and startups. These will be presented at a special lightning session in the workshop. Please contact the workshop organizers (podobas at kth.se) if you are interested in participating in this event.



 -----------------------  ORGANIZATION -------------------------



ORGANIZERS:

  Artur Podobas (KTH, Sweden)

  Kentaro Sano (RIKEN, Japan)

  Jason Anderson (University of Toronto, Canada)



PROGRAM COMMITTEE:

  Ahsan Javed Awan (Ericsson, Sweden)

  Ahmed Heman (KTH, Sweden)

  Cheng Tan (Microsoft, USA)

  Christian Hochberger (TU Darmstadt, Germany)

  Elliot Delaye (AMD/Xilinx, USA)

  Hayden So (HKU, Hong Kong)

  Jens Domke (RIKEN, Japan)

  Markus Weinhardt (HS-Osnabrueck, Germany)

  Masato Motomura (TiTech, Japan)

  Nakashima Yasuhiko (NAIST, Japan)

  Takuya Kojima (Univ. of Tokyo, Japan)





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Artur Podobas
Assistant Professor
Department of Computer Science
School of Electrical Engineering and Computer Science
KTH Royal Institute of Technology
Stockholm, Sweden
URL: https://www.kth.se/profile/podobas