[hpc-announce] ISC 2023 Call for Papers (Deadline: December 23, 2022)

Abhinav Bhatele bhatele at cs.umd.edu
Fri Nov 4 09:43:38 CDT 2022



The ISC research paper sessions provide world-class opportunities for
engineers and scientists in academia, industry, and government to present
and discuss issues, trends, and results that will shape the future of High
Performance Computing (HPC), machine learning, data analytics and quantum

The ISC organizers will again sponsor the Hans Meuer Award, which
recognizes the most outstanding research paper, selected by members of the
research papers committee. The Hans Meuer Award includes a cash prize of
3,000 Euros for the paper’s authors.

Submitted research paper proposals will be reviewed by the ISC 2023
Research Papers Committee, which is headed by Abhinav Bhatele, University
of Maryland, as Chair, and Jeff Hammond, NVIDIA, Inc., as Deputy Chair.

  Full Submission Deadline: December 23, 2022 23:59 AoE
  Author Rebuttals: February 11 - 15, 2023
  Notification of Acceptance: February 24, 2023
  Camera-Ready Submission: March 17, 2023 23:59 AoE
  Final Presentation Slides in PDF due: to be announced
  Short Pre-recorded Video due: May 1, 2023 23:59 AoE
  Research Paper Sessions: Monday May 22 – Wednesday May 24, 2023

  Research Papers Chair: Abhinav Bhatele, University of Maryland, USA
  Research Papers Deputy Chair: Jeff Hammond, NVIDIA, Inc., Finland
  Proceedings Chair: Marc Baboulin, Université Paris-Saclay, France
  Proceedings Deputy Chair: to be announced


The Research Papers Committee encourages the submission of high-quality
papers reporting original work in theoretical, experimental, and industrial
research & development. The ISC submission process will be divided into
five tracks this year, as follows:

*Architectures, Networks, and Storage*
- Next-generation processors and accelerators for HPC
- Extreme heterogeneous chips/chiplets for HPC beyond exascale
- The future of computing beyond Moore's Law
- Network technology & architecture
- Domain-specific architectures / accelerators
- Memory technologies & hierarchies
- Storage architectures & file systems
- Scalable architectures for big data and data science
- Exascale computing
- Distributed / disaggregated resources / systems

*HPC Algorithms & Applications*
- Novel algorithms for HPC
- Algorithmic-based fault tolerance
- Communication-reducing & synchronization-reducing algorithms
- Time-space trade-offs in algorithms and applications
- Extreme-scale applications
- Energy-efficient algorithms & applications
- Convergence of simulations & big data
- Application scalability on future architectures
- Data-intensive applications
- Coupled simulations
- Implementations on GPUs & accelerators
- In-situ data analysis

*Programming Environments & Systems Software*
- Parallel programming models, languages, and compilers
- Tools and libraries for performance & productivity at scale
- Scalable application frameworks
- Runtime systems for HPC
- Resilience / system robustness
- Operating systems & workload management
- Tools for system monitoring & administration
- Power, energy management, and scheduling
- Workflow management
- Databases

*Machine Learning, AI, & Quantum Computing*
- AI/Machine learning & HPC
- HPC system design for AI & machine learning
- I/O, domain-specific languages, and tools for scalable machine learning
- Applied machine learning studies
- Uncertainty quantification
- HPC for parallel/distributed deep learning
- Explainable AI and FAIR Principles for ML and data management
- Quantum computing architecture, algorithms, and software
- Quantum computing & HPC
- Other cutting-edge or emerging HPC technologies

*Performance Modeling, Evaluation, & Analysis*
- Performance models and prediction
- Performance engineering and optimizations
- Performance measurement tools and techniques
- Power consumption measurement and modeling
- Performance analysis and visualization tools
- Simulations for performance modeling and prediction
- Workflow modeling

Note: Submissions on other innovative aspects of high performance computing
are also welcome. You will be asked to pick a primary and a secondary track
from the five above for your submission.

For more details, please visit:

Abhinav Bhatele, Research Papers Chair
Jeff Hammond, Research Papers Deputy Chair

Abhinav Bhatele, cs.umd.edu/~bhatele
Department of Computer Science, University of Maryland, College Park

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