[hpc-announce] Accelerator Architecture in Computational Biology and Bioinformatics workshop (ISCA 2022 date change)

leonid.yavits at nububbles.com leonid.yavits at nububbles.com
Wed Mar 23 02:56:32 CDT 2022



4th Accelerator Architecture in Computational Biology and Bioinformatics workshop (AACBB-2022)

June 18th 2022 


In conjunction with 49th IEEE International Symposium on Computer Architecture 

New York City, New York, USA


Workshop website



Submission link



Submission deadline

April 20, 2022, EoD AoE



May 5, 2022


Over the last decade, the advent of high-throughput sequencing techniques brought an exponential growth in sequenced data. 

At the same time, the single-thread performance continued to improve by only a few percent point annually. 

The growing gap between the performance demand to performance supply became a significant challenge in the path to scientific discovery. 

The computational bottleneck of genome analysis pipelines became even more apparent during the ongoing Covid-19 pandemic, where 

fast and reliable virus detection and classification tools have been critical for the worldwide genomic surveillance system. 


The gap between the performance of a conventional computer architecture and the biological data processing requirements is growing. 

For example, assembling a human genome from 3rd generation sequenced data may require hundreds of CPU hours. 

Hence, computational biology and bioinformatics will have to rely on hardware accelerators to allow processing to keep up with the exploding amount of sequenced data.


In a typical application, the dominant portion of the runtime is spent in a small number of computational kernels, 

making it an excellent target for hardware acceleration. The combination of increasingly large datasets and high performance 

computing requirements make computational biology a prime candidate to benefit from accelerator architecture research. 

Potential directions include 3D integration, near-data processing, in-data processing and reconfigurable architectures.


This workshop will focus on architecture and design of hardware accelerators for computational biology and bioinformatics problems. 

We plan to present and discuss a variety of acceleration techniques, accelerator architectures and their implications on the development 

of computational biology. This year, we plan to extend the industry angle, by providing a keynote and invited talks from leading industry research specialists.



List of Topics

This workshop focuses on architecture and design of hardware and software accelerators for computational biology and bioinformatics problems.

Topics of interest include, but are not limited to the following:

   - Hardware and software algorithms/applications in the fields of computational biology, such as (but not limited to):

        - Bioinformatics

        - Genomics

        - Proteomics

        - Protein structure prediction

        - Covid-19 pandemic

    - Bioinformatics and computational biology accelerator architecture and design based on (but not limited to):

        - 3D memory-logic stack 

        - Near-data (in-memory) processing

        - In-data processing

        - FPGAs

        - Reconfigurable architectures 

    - Emerging memory technologies and their impact on bioinformatics and computational biology

    - Impact of bioinformatics and biology applications on computer architecture research

    - Bioinformatics and computational biology-inspired hardware/software trade-offs


Keynote Speakers

    - Tajana Rosing, Prof of Computer Science and Engineering, director of System Energy Efficiency Lab, UCSD

    - Onur Mutlu, Prof of Computer Science, Zurich ETH and CMU 




Program Committee

    - Ananth Kalyanaraman, WSU

    - Can Alkan, Bilkent University

    - Engin Ipek, University of Rochester

    - Jason Cong, UCLA

    - Mattan Erez, UT Austin

    - Mircea Stan, UVA

    - Onur Mutlu, ETH/CMU

    - Ran Ginosar, Technion

    - Ronnie Ronen, Technion

    - Yuan Xie, UCSB 

Organizing committee

    - Leonid Yavits* (leonid.yavits at gmail.com)

    - Yatish Turakhia^ (yturakhia at eng.ucsd.edu) 

* Department of Engineering, Bar Ilan University 

^ Department of Electrical and Computer Engineering, University of California, San Diego


Important Notes

Presenting a paper in the workshop does not preclude publication in other venues



All questions about submissions should be emailed to Leonid Yavits (leonid.yavits at gmail.com) 






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