[hpc-announce] [CFP] IA^3 2022: 12th SC Workshop on Irregular Applications: Architectures and Algorithms

Tumeo, Antonino Antonino.Tumeo at pnnl.gov
Sun Jul 17 11:36:28 CDT 2022

[Please accept our apologies for multiple postings.]

IA^3 2022
12th Workshop on Irregular Applications: Architectures and Algorithms
November 18, 2022
Dallas, TX
In conjunction with SC22
In cooperation with IEEE


Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, sparse matrices, deep nets, tables, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.

Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Emerging supercomputing applications are moving towards a convergence of scientific simulation, data analytics, and learning algorithms, mixed in various ways. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years.

This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to:

- Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors 
- Network architectures and interconnect (including high-radix networks, optical interconnects) 
- Novel memory architectures and designs (including processors-in memory) 
- Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing) 
- Modeling, simulation and evaluation of novel architectures with irregular workloads 
- Innovative algorithmic techniques 
- Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.)
- Impact of irregularity on machine learning approaches
- Parallelization techniques and data structures for irregular workloads
- Data structures combining regular and irregular computations (e.g., attributed graphs)
- Approaches for managing massive unstructured datasets (including streaming data) 
- Languages and programming models for irregular workloads
- Library and runtime support for irregular workloads
- Compiler and analysis techniques for irregular workloads
- High performance data analytics applications (including graph databases and solutions that combine graph algorithms with machine learning) 
- Applications that integrate scientific simulation, data analytics, and learning, and require efficient execution of irregular workloads

Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation.


Abstract Submission:   August 5, 2022 (AoE) 
Position or Regular Paper Submission: August 11, 2022 (AoE)
Notification: September 9, 2022
Camera-ready: October 10, 2022
Workshop: November 18, 2022


Submission site: https://submissions.supercomputing.org

Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four (4) pages for position papers (excluding references).
Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix.

The templates are available at: 

The proceedings of the workshop will be published in the IEEE Digital Library in cooperation with IEEE Computer Society


Antonino Tumeo, PNNL, antonino.tumeo at pnnl.gov
Marco Minutoli, PNNL, marco.minutoli at pnnl.gov
John Feo, PNNL, john.feo at pnnl.gov
Vito Giovanni Castellana, PNNL, vitogiovanni.castellana at pnnl.gov


Nesreen Ahmed, Intel, US
Johnathan Alsop, AMD, US
Jonathan Beard, ARM, US 
Michela Becchi, North Carolina State University, US
Sanjukta Bhowmick, University of North Texas, US
Erik Boman, Sandia National Laboratories, US 
David Brooks, Harvard University, US 
Prerna Budhkar, Intel, US 
Anastasiia Butko, Lawrence Berkeley National Laboratory, US 
Eric Cheng, Laboratory of Physical Sciences, US 
Salvatore Di Girolamo, ETH Zurich, CH 
Oded Green, NVIDIA, US 
Rajiv Gupta, University of California, Riverside, US
Peter M. Kogge, University of Notre Dame and Lucata, US 
John Leidel, Tactical Computing Labs, US 
Kamesh Madduri, Pennsylvania State University, US 
Tim Mattson, Intel, US 
José Moreira, IBM TJ Mattson, US 
Miquel Moretó, Barçelona Supercomputing Center, ES
Maxim Naumov, Meta, US 
Fanny Nina-Paravecino, Microsoft, US 
Marziyeh Nourian, University of Chicago, US 
Roger Pearce, Lawrence Livermore National Laboratory, US 
Bradley Rees, NVIDIA, US 
Alejandro Rico, ARM, US 
Thomas B Rolinger, Laboratory of Physical Sciences, US 
Kentaro Sano, RIKEN, JP
Sudip Seal, Oak Ridge National Laboratory, US 
John Shalf, Lawrence Berkeley National Laboratory, US 
Julian Shun, Massachusetts Institute of Technology, US 
Edgar Solomonik, University of Illinois at Urbana-Champaign
Tyler Sorensen, University of California, Santa Cruz, US 
Ruud van der Pas, Oracle, US 
Ana Lucia Varbanescu, University of Amsterdam, NL 
Flavio Vella, University of Trento, IT

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