[hpc-announce] Reconfigurable Architectures Workshop 2022 Call for Papers (Deadline Ext'd)

[Brian Veale]

               CALL FOR PAPERS
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     29th Reconfigurable Architectures Workshop
                            RAW 2022
     Lyon, France, May 30 – 31, 2022

SUBMISSION DEADLINE EXTENDED TO February 11, 2022

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QUICK LINK:
         Web site: http://raw.necst.it/
         Submissions: https://easychair.org/conferences/?conf=raw2022
IMPORTANT DATES:
         Submission deadline February 11 2022
         Decision notification February 18, 2022
         Conference: May 30-31, 2022
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RAW 2022

The 29th Reconfigurable Architectures Workshop (RAW 2022) will be held in
Lyon in May 2022.
RAW 2022 is associated with the 36th Annual IEEE International Parallel &
Distributed Processing
Symposium (IEEE IPDPS 2022) and is sponsored by the IEEE Computer Society
and the Technical Committee
on Parallel Processing. The workshop is one of the oldest platforms and a
vibrant forum for researchers
to present new ideas, fresh results, and on-going research into both
theoretical and practical advances
including novel innovations in Reconfigurable Computing. A reconfigurable
computing environment is
characterized by the ability of underlying hardware architectures or
devices to rapidly alter (often on
the fly) the functionalities of their components and the interconnection
between them to suit the
problem at hand. The area has a rich theoretical tradition and wide
practical applicability. There are
several commercially available reconfigurable platforms (FPGAs and
coarse-grained devices) and many
modern applications (including embedded systems and HPC) use reconfigurable
subsystems. An appropriate
mix of theoretical foundations and practical considerations, including
algorithms architectures,
applications, technologies and tools, is essential to fully exploit the
possibilities offered by
reconfigurable computing. The Reconfigurable Architectures Workshop aims to
provide a forum for
creative and productive interaction for researchers and practitioners in
the area. This year the
workshop will also provide a platform for work in progress.

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SUBMISSION OF PAPERS

Submissions should be a complete manuscript or, in special cases, may be a
summary of relevant work.
Authors are highly encouraged to submit a demo of their work and provide
source code/relevant material
to reproduce the paper’s results. Manuscripts for full papers should not
exceed 8 single-spaced,
double-column pages using 10-point font on 8.5 x 11 inch pages (IEEE
conference style) including
references, figures and tables. Manuscripts for short papers should not
exceed 4 single-space,
double-column pages. Papers are to be submitted through EasyChair.
Submitted papers should not have
appeared in or be under consideration for another workshop, conference or
journal. All papers must be
submitted electronically in PDF format. Submissions can be made through:
. the RAW2022 web site: http://raw.necst.it/
. EasyChair: https://easychair.org/conferences/?conf=raw2022

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IMPORTANT DATES
         Submission deadline February 11 2022
         Decision notification: February 18, 2022
         Conference: May 30-31, 2022
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TOPICS OF INTEREST
Hot Topics
- Configurable Cloud
- Heterogeneous Computing in Data Centers
- Accelerating Data Center Workloads
- FPGA-based Deep Learning
- Accelerating Genomic Computations
- Accelerating Data Analytics
- Reconfigurable Computing in the IoT era
- Organic Computing, BiologicallyInspired Solutions
- Applications in Finance
Architecture & CAD
- Algorithmic Techniques and Mapping
- Emerging Technologies (optical models, 3D Interconnects, devices)
- Reconfigurable Accelerators
- Embedded Systems and DomainSpecific solutions (Digital Media, Gaming,
Automotive applications)
- FPGA-based MPSoC and Multicore
- Distributed Systems & Networks
- Wireless and Mobile Systems
- Critical issues (Security, Energy efficiency, Fault-Tolerance)
Runtime/System Management
- Runtime Reconfiguration Models
- Autonomic computing systems
- Operating Systems and High-Level Synthesis
- High-Level Design Methods (HW/SW co-design, Compilers)
- System Support (Soft processor programming)
- Runtime Support
- Reconfiguration Techniques (reusable artifacts)
- Simulation and Prototyping (performance analysis, verification tools)
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ORGANIZERS

Workshop Chair
         Marco D. Santambrogio, Politecnico di Milano, Italy

Program Chair
         Lana Josipović, EPFL, Switzerland

Steering Committee
         Juergen Becker, Karlsruhe Insttute of Technology, Germany
         Viktor K. Prasanna, University of Southern California, USA
         Ramachandran Vaidyanathan, Louisiana State University, USA

Publicity
         Brian Veale, IBM, USA
         Yukinori Sato, Toyohashi University of Technology, Japan
         Dirk Stroobandt, Ghent University, Belgium