[hpc-announce] CFP: Workshop HPCMALL 2022: Malleability Techniques Applications in High-Performance Computing. to be held at ISC2022

[JESUS CARRETERO PEREZ]

WORKSHOP. HPCMALL 2022: Malleability Techniques Applications in
High-Performance Computing
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ISC 2022 - Congress Center Hamburg (CCH)
Messe Hamburg, Germany, June 2, 2022

Workshop website      https://www.admire-eurohpc.eu/events/hpcmall/
Submission link https://easychair.org/conferences/?conf=hpcmall2022

Important Dates
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Abstract submission:  March 1st 2022
Preliminary version of papers:  March 7th 2022
Notification:  April 6th, 2022
Final version of the paper: April 21st, 2022


Workshop Chairs
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Prof. Jesus Carretero, University Carlos III of Madrid, Spain.
Prof. Martin Schulz, Technical University of Munich, Germany.
Dr. Estela Suarez, Juelich Supercomputing Centre, Forschungszentrum
Juelich GmbH, Germany.



Description of the workshop
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The current static usage model of HPC systems is becoming increasingly
inefficient. This is driven by the continuously growing complexity and
heterogeneity of system architectures, in combination with the
increased usage of coupled applications, the need for strong scaling
with extreme scale parallelism, and the increasing reliance on complex
and dynamic workflows. As a consequence, we see a rise in research on
malleable systems, middleware software and applications, which can
adjust resource usage dynamically in order to extract a maximum of
efficiency. By providing an intelligent global coordination of
resources usage, through runtime scheduling of computation, network
usage and I/O across all components of the system architecture,
malleable HPC systems can maximize the exploitation of their
resources, while at the same time minimizing the makespan of
applications in many, if not most, cases. Of particular concern is the
emerging class of data-intensive applications and their interaction
with classic simulation workloads, driven by the growing need to
process extremely large data sets. However, uncoordinated file access
in combination with limited bandwidth make the I/O system a serious
bottleneck. Emerging multi-tier storage hierarchies come with the
potential to remove this barrier, but maximizing performance still
requires careful control to avoid congestion. Malleability allows
systems to dynamically adjust the computation and storage needs of
applications, on the one side, and the global system on the other.
Such malleable systems, however, face a series of fundamental research
challenges, including: who initiates changes in resource availability
or usage? How is it communicated? How to compute the optimal usage?
How can applications cope with dynamically changing resources? What
should malleable programming models and abstractions look like? How to
design resource management frameworks for malleable systems? Which
resources benefit from malleability and which (if any) should still be
managed statically?
In order to address these challenges, the HPCMALL workshop will bring
together researchers from diverse areas of HPC that are impacted or
actively pursuing malleability concepts, from application developers
to system architects, from programming model to system software
researchers. The workshop will provide a lively discussion forum for
researchers working in HPC and pursuing the concepts of and around
malleability.

Topics:
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We are looking for original high-quality research and position papers
on applications, services, and system software for malleable
high-performance computing systems. Topics of interest include, but
are not limited to:

* System and system architecture considerations in designing malleable
architectures.
* Emerging software designs to achieve malleability in
high-performance computing.
* High-level parallel programming models and programmability
techniques to improve applications malleability.
* Run-time techniques to provide malleable execution models for
computation, communication and I/O.
* Resource management frameworks and interfaces supporting malleable
scheduling, resource allocations and application execution.
* Computing and I/O scheduling algorithms providing and/or exploiting
static or dynamic malleability.
* Use of AI and ML techniques to steer malleability in systems and applications.
* Ad-hoc storage systems and I/O scheduling techniques helping I/O malleability.
* Support for malleable execution of applications in performance,
debugging and correctness tools.
* Energy efficiency and malleability (applications, over-provisioned
systems wrt. power/energy, storage systems, etc.).
* Experiences and use cases applying malleability to HPC applications.

Submission Guidelines
----------------------
Papers will be published  together with ISC proceedings.
We will allow both regular full page research papers (maximum 18
pages, including figures and references), as well as 8-9 page short or
position papers, in order to cover both more mature approaches in the
area as well as hot and novel concepts in their early stages.
A Journal Special Issue will be published in The International Journal
of High Performance Computing Applications (IJHPCA).  The special
issue will have an open CFP, but extended versions of the best papers
accepted at HPCMALL 2022 will be invited for publication. All papers
will undergo the usual peer-review process of IJHPCA.

Paper submissions are required to be formatted using LNCS style (see
Springer’s website):
- Single-column format
- Maximum 18 pages (including figures and references)
- Use Springer’s LaTeX document class or Word template (see Springer’s
Proceedings Guidelines)
- Papers must be suitable for double-blind review (see ISC High
Performance Double-Blind Review Guidelines)
- The PC reserves the right to reject incorrectly formatted papers

Papers cannot have been previously published or simultaneously under review.


Workshop Program Committee
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Fabio Affinito. Cineca. Italy

Alexander Antonov. Moscow State University, Russia

Jean-Baptiste Besnard. ParaTools SAS. France

Andre Brinkmann. Johannes Gutenberg-Universität Mainz. Germany

Iacopo Colonnelli,  University of Totino. Italy.

Norbert Eicker. JSC and Univ. Wuppertal. Germany.

Hamid Mohammadi Fard. Technical University of Darmstadt. Germany

Hal Finkel, Department of Energy, USA.

Javier Garcia Blas. Carlos III University. Spain

Michael Gerndt. Technical University of Munich. Germany.

Balazs Gerofi. RIKEN. Japan.

Emmanuel Jeannot. INRIA. France.

Michael Klemm.  AMD. Germany.

Masaki Kondo. Keio University. Japan.

Erwin Laure. MPCDF. Germany.

Stefano Markidis. KTH. Sweden.

Thomas Moschny. PARTEC. Germany.

Ramon Nou. Universitat Politècnica de Catalunya. Spain

Ariel Oleksiak.  Poznan Supercomputing and Networking Center. Poland.

David E. Singh. Universidad Carlos III de Madrid. Spain

Martin Schreiber  University of Grenoble-Alpes.  France

Sameer Shende. ParaTools SAS. USA.

Miwako Tsuji. RIKEN AICS. Japan.

Marc André Vef. Johannes Gutenberg-Universität Mainz. Germany.

Carlos A. Varela. Rensselaer Polytechnic Institute. USA.

Vladimir Voevodin. Moscow State University. Russia.

Mohamed Wahib. AIST/TokyoTech. OIL Japan.

Josef Weidendorfer. Technical University of Munich. Germany

Michele Weiland. EPCC- The University of Edinburgh. UK.

Roman Wyrzykowski. Czestochowa University of Technology. Poland.


-- 
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Prof. Jesus Carretero
Computer Architecture Professor
Computer Science and Engineering Dep. University Carlos III of Madrid
Avda. Universidad 30,  28911 Leganes, Madrid, Spain

Email: jesus.carretero at uc3m.es
Tel: +34 916249458.  Fax: +34 916249129
Web: http://arcos.inf.uc3m.es/~jcarrete
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