[hpc-announce] [CFP][DFM22] — International Workshop on Data Flow Models for Extreme-Scale Computing

[Stéphane Zuckerman]

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*           12th IEEE International Workshop on Data Flow Models        *
*               and Extreme-Scale Computing (DFM 2022)                  *
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*         Hosted as part of COMPSAC 2021, June 27—July 1, 2022          *
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* Note: depending on the sanitary context, the event may be held in a   *
* hybrid fashion.                                                       *
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* The DFM workshop aims to highlight advancements to event-driven and   *
* data-driven models of computation for extreme scale computing,        *
* parallel and distributed computing for high-performance computing,    *
* and high-end embedded and cyber-physical systems. It also aims at     *
* fostering exchanges between dataflow practitioners, both at the       *
* theoretical and practical levels.                                     *
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*                           Important Dates                             *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
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* Workshop papers due:                                 7 April, 2022    *
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* Workshop paper notifications:                       15   May, 2022    *
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* With the advent of true many-core systems, it has become unreasonable *
* to solely rely on control-based parallel models of computation to     *
* achieve high scalability. Dataflow-inspired models of computation,    *
* once discarded by the sequential programming crowd, are once again    *
* considered serious contenders to help increase programmability,       *
* performance, and scalability in highly parallel and extreme scale     *
* systems, but also power and energy efficiency, as they (at least      *
* partially) relieve the parallel application programmer from performing*
* tedious and perilous synchronization bookkeeping, but also provide    *
* clear scheduling points for the system software and hardware. They are*
* also an invaluable tool for high-end embedded computing to deal with  *
* real-time constraints. However, to reach such high scalability levels,*
* extreme scale systems rely on heterogeneity, hierarchical memory      *
* subsystems, etc.Meanwhile, legacy programming and execution models,   *
* such as MPI and OpenMP, add asynchronous and data-driven constructs   *
* to their models, all the while trying to take into account the very   *
* complex hardware targeted by parallel applications. Consequently,     *
* programming and execution models, trying to combine both legacy       *
* control flow-based and dataflow-based aspects of computing, have also *
* become increasingly complex to handle. Developing new models and their*
* implementation, from the application programmer level, to the system  *
* level, down to the hardware level is key to provide better data- and  *
* event-driven systems which can efficiently exploit the wealth of      *
* diversity that composes current high-performance systems, for extreme *
* scale parallel computing. To this end, the whole stack, from the      *
* application programming interface down to the hardware must be        *
* investigated for programmability, performance, scalability, energy    *
* and power efficiency, as well as resiliency and fault-tolerance.      *
* *
* Researchers and practitioners all over the world, from both academia  *
* and industry, working in the areas of language, system software, and  *
* hardware design, parallel computing, execution models, and resiliency *
* modeling are invited to discuss state of the art solutions, novel     *
* issues, recent developments, applications, methodologies, techniques, *
* experience reports, and tools for the development and use of dataflow *
* models of computation. Topics of interest include, but are not lim-   *
* ited to, the following:                                               *
* *
* - Programming languages and compilers for existing and new languages— *
*   in particular single-assigned and functional languages              *
* *
* - System software: Operating systems, runtime systems                 *
* *
* - Hardware design: ASICs and reconfigurable computing (FPGAs)         *
* *
* - Resiliency and fault-­tolerance for parallel and distributed systems*
* *
* - New dataflow inspired execution models — in particular strict and   *
*   non-strict models                                                   *
* *
* - Hybrid system design for control-flow and data-flow based systems   *
* *
* - dataflow-based AI architectures and accelerators                    *
* *
* - Dataflow-inspired optimizations to ML frameworks, graphs, etc.      *
* *
* *
* - Position papers on the future of dataflow in the era of many-core   *
*   systems and beyond                                                  *
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*                           Important Dates                             *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* *
* Workshop papers due:                                 7 April, 2022    *
* *
* Workshop paper notifications:                       15   May, 2022    *
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* Authors are invited to submit original, unpublished research work, as *
* well as industrial practice reports. Simultaneous submission to other *
* publication venues is not permitted.  In accordance with IEEE policy, *
* submitted manuscripts will be checked for plagiarism. Instances of    *
* alleged misconduct will be handled according to the IEEE Publication  *
* Services and Product Board Operations Manual.                         *
* *
* Please note that in order to ensure the fairness of the review        *
* process, COMPSAC follows the double-blind review procedure. Therefore *
* we kindly ask authors to remove their names, affiliations and contacts*
* from the header of their papers in the review version. Please also    *
* redact all references to authors’ names, affiliations or prior works  *
* from the paper when submitting papers for review. Once accepted,      *
* authors can then include their names, affiliations and contacts in    *
* the camera-ready revision of the paper, and put the references to     *
* their prior works back.                                               *
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* Formatting                                 *
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* Workshop papers are limited to 6 pages. Page limits are inclusive of  *
* tables, figures, appendices, and references. Workshop papers can add  *
* an additional 2 pages with additional page charges ($250USD/page).    *
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-- 
Maître de conférences / Associate Professor
Chargé de mission accompagnement jeunes chercheurs — laboratoire ETIS
Directeur des études de première année — IUT GEII (Neuville)
Laboratoire ETIS, UMR 8051, CY Cergy Paris Universités, ENSEA, CNRS, F-95000, Cergy, France