[hpc-announce] CFP: (Deadline Extended to Feb 1st) AsHES 2021, The Eleventh International Workshop on Accelerators and Hybrid Emerging Systems

[SIMON GARCIA DE GONZALO]

DEADLINE EXTENDED TO FEB. 1ST!
The Eleventh International Workshop on Accelerators and Hybrid Emerging 
Systems (AsHES)
https://pmodels.github.io/ashes-www/2021/index.html
May 17th, 2021

With PARCO Special Issue

To be held in conjunction with 35th IEEE International Parallel and 
Distributed Processing Symposium
Portland, Oregon USA

Workshop Scope and Goals
========================================
The current computing landscape has gone through an ever-increasing rate 
of change and innovation. This change has been driven by the relentless 
need to improve the energy-efficient, memory, and compute throughput at 
all levels of the architectural hierarchy. Although the amount of data 
that has to be organized by today's systems posed new challenges to the 
architecture, which can no longer be solved with classical, homogeneous 
design. Improvements in all of those areas have led Heterogeneous 
systems to become the norm rather than the exception.

Heterogeneous computing leverages a diverse set of computing (CPU, GPU, 
FPGA, TPU ...) and Memory (HBM, Persistent Memory, Coherent PCI 
protocols, etc ..), hierarchical storage systems and units to accelerate 
the execution of a diverse set of applications. Emerging and existing 
areas such as AI, BigData, Cloud Computing, Edge-Computing, Real-time 
systems, High-Performance Computing, and others have seen a real benefit 
due to Heterogenous computer architectures. These new heterogeneous 
architectures often also require the development of new applications and 
programming models, in order to satisfy these new architectures and to 
fully utilize these capacities. This workshop focuses on understanding 
the implications of heterogeneous designs at all levels of the computing 
system stack, such as hardware, compiler optimizations, porting of 
applications, and developing programming environments for current and 
emerging systems in all the above-mentioned areas. It seeks to ground 
heterogeneous system design research through studies of application 
kernels and/or whole applications, as well as shed light on new tools, 
libraries and runtime systems that improve the performance and 
productivity of applications on heterogeneous systems.

The goal of this workshop is to bring together researchers and 
practitioners who are at the forefront of Heterogeneous computing in 
order to learn the opportunities and challenges in future Heterogeneous 
system design trends and thus help influence the next trends in this 
area.


Topics of interest for the full paper (8 - 10 pages) track submissions 
include (but are not limited to):

* Strategies for programming heterogeneous systems using high-level 
models such as OpenMP, OpenACC, SYCL, low-level models such as OpenCL, 
CUDA;
* Methods and tools to tackle challenges from heterogeneity in AI/ML/DL, 
BigData, Cloud Computing, Edge-Computing, Real-time Systems, and 
High-Performance Computing;
* Strategies for application behavior characterization and performance 
optimization for accelerators;
* Techniques for optimizing kernels for execution on GPGPU, FPGA, TPU, 
and emerging heterogeneous platforms;
* Models of application performance on heterogeneous and accelerated HPC 
systems;
* Compiler Optimizations and tuning heterogeneous systems including 
parallelization, loop transformation, locality optimizations, 
Vectorization;
* Implications of workload characterization in heterogeneous and 
accelerated architecture design;
* Benchmarking and performance evaluation for heterogeneous systems at 
all level of the system stack;
* Tools and techniques to address both performance and correctness to 
assist application development for accelerators and heterogeneous 
processors;
* System software techniques to abstract application domain-specific 
functionalities for accelerators;

A short paper track (maximum of 6 pages) has been added to this year’s 
program to highlight early investigations of innovative ideas in 
emerging selected topics such as:
* Innovative use of heterogeneous computing in AI for science or 
optimizations for AI
* Heterogeneous computing at Edge
* Design and use of domain-⁠specific functionalities on accelerators

Important Dates (AoE)
========================================
Paper Submission:   Feb. 1st, 2021(AoE) NEW!
Paper Notification: Feb. 20, 2021 (AoE)

Proceedings
========================================
The proceedings of this workshop will be published electronically 
together with IPDPS proceedings via the IEEE Xplore Digital Library.

Papers Submission Guidelines
========================================
Papers should present original research and should provide sufficient 
background material to make them accessible to the broader community.

Regular paper track submitted manuscripts may not exceed 10 
single-spaced double-column pages using 10-point size font on 8.5x11 
inch pages (IEEE conference style), including figures, tables, and 
references. See the style templates for latex or word for details.

Short paper track submitted manuscripts follow the same instructions as 
the regular manuscript but may not exceed 6 pages.

Submissions will be judged based on relevance, significance, 
originality, correctness, and clarity.

Submission site: https://easychair.org/conferences/?conf=ashes2021

Journal Special Issue
========================================
The best papers of AsHES 2021 will be invited to a Special Issue on
Topics on Heterogeneous Computing of the Elsevier International Journal
on Parallel Computing (PARCO).

Steering Committee
========================================
Pavan Balaji, Argonne National Laboratory, USA
Yunquan Zhang, Chinese Academy of Sciences, China
Satoshi Matsuoka, Tokyo Institute of Technology, Japan
Jiayuan Meng, Argonne National Laboratory, USA
Xiaosong Ma, Qatar Computing Research Institute, Qatar
Barbara Chapman, Stony Brook University, USA
Guang R. Gao, University of Delaware, USA
Xinmin Tian, Intel, USA
Michael Wong, Codeplay, UK
James Dinan, Intel Corporation
Sunita Chandrasekaran, University of Delaware, USA
Antonio J. Peña, Barcelona Supercomputing Center, Spain

General Chair
========================================
Min Si, Argonne National Laboratory, USA

Program Co-⁠Chairs
========================================
Lena Oden, FernUni Hagen, Germany
Simon Garcia de Gonzalo, Barcelona Supercomputing Center, Spain

Program Committee
========================================
Guray Ozen, NVIDIA, USA
Adrián Castelló, Universitat Jaume I, Spain
Leonel Toledo, Barcelona Supercomputing Center, Spain
Pedro Valero-⁠Lara, Cray, a Hewlett Packard Enterprise company, USA
John Leidel, Texas Tech University, USA
Paul F. Baumeister, Jülich Supercomputing Centre
Seyong Lee, Oak Ridge National Laboratory, USA
Ashwin M. Aji, AMD, USA
Stephen Olivier, Sandia National Laboratories, USA
Gabriele Jost, NASA Ames Research Center/⁠CSRA, USA
Guido Juckeland, Helmholtz-⁠Zentrum Dresden-⁠Rossendorf (HZDR), Germany
Huimin Cui, Institute of Computing Technology, CAS, China
Gaurav Mitra, Texas Instruments Inc., USA
Nikela Papadopoulou, National Technical University of Athens, Greece
Bronis de Supinski, Lawrence Livermore National Laboratory, USA

Questions?
========================================
Please send any queries about the AsHES workshop to ashes at mcs.anl.gov

Dr. Simon Garcia De Gonzalo
Postdoctoral Researcher and STARS 2020 Fellow
Accelerators and Communications for HPC
Barcelona Supercomputing Center (BSC)
simon.garcia at bsc.es

http://bsc.es/disclaimer