[hpc-announce] Call for Papers International Workshop on Machine Learning for Software Hardware Co-Design (MLSH'21)

Joseph B Manzano josbry27 at gmail.com
Mon Aug 16 20:17:09 CDT 2021

                                                     Call for Papers

                                International Workshop on Machine Learning for

                                                Software Hardware
Co-Design (MLSH'21)

                                                                Virtual Event

                                                Held in Conjunction with PACT 21


Important Dates

Paper submission: August 27th (AOE), 2021 Paper notification:
September 10th, 2021

Camera-ready: September 20th, 2021

Workshop date: TBD


As Machine Learning (ML) continues to permeate all areas of computing,
software system designers and software stack developers are adopting
ML solutions and designs to solve challenging problems presented in
their areas; especially in areas like optimization and hardware
design. ML is increasingly being used to solve a diverse set of
problems such as the design of cost models, code optimization
heuristics, efficient search space exploration, automatic
optimization, and program synthesis.

Designing accurate machine learning models, feature engineering,
verification, and validation of obtained results and selecting and
curating representative training data are all examples of challenging
but important problems in this area that are actively being explored
by a large community of researchers in industry and academia. This
workshop provides a great venue for the international research
community to share ideas and techniques to apply machine learning to
system challenges with a focus on the software stack and hardware.


We will solicit papers on topics including, but not limited to, the
following areas:

- ML for the software stack

     * Heuristics and cost model construction.

     * Optimization space exploration.

     * Automatic code optimization.

     * Bug detection.

     * Program synthesis.

     * Program and code representation.

     * Important training paradigms.

- ML for hardware

     * ML models for optimal configuration for FPGA.

     * Load balancing between CPU and accelerators (e.g. GPUs, TPUs, etc).

     * ML models to improve computer architecture design.

     * Analysis and techniques to define meaningful representation

(features) for compilers and hardware.

- Training data

     * Exploring the availability or generation of efficient training
data for compilers and hardware.

     * Utilizing graph-based data for machine learning.

Submission Guidelines

We invite both full-length research papers and short research papers.

The submitted paper should not exceed the page limit (8 pages for
full-length and 4 pages for short papers) and should follow the IEEE
conference proceedings templates. The page limit applies to all
content NOT including references, and there is no page limit for

The submission will be reviewed by at least three program committee
members and should not have published in or under review for another
venue. Accepted papers will be published in our online proceedings.

Submit your paper using this link https://easychair.org/conferences/?conf=mlsh21

How to Attend?

All the presentations will be virtual.

Program Committee


Past Editions

MLSH'20: http://groups.csail.mit.edu/commit/mlsh/2020/


- Eun Jung (EJ) Park (Los Alamos National Laboratory).

- Riyadh Baghdadi (New York University and Massachusetts Institute of

- Joseph Manzano (Pacific Northwest National Laboratory).

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