[hpc-announce] CALL FOR PAPERS: Micromachines (Impact Factor 2.53) Special Issue "Network-on-Chip and Application"

gnkhan at ee.ryerson.ca gnkhan at ee.ryerson.ca
Tue Apr 6 12:02:55 CDT 2021

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CALL FOR PAPERS: Micromachines (Impact Factor 2.53)
Special Issue "Network-on-Chip and Application"

Micromachines (Impact Factor 2.53) Special Issue "Network-on-Chip and

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs
to the section "Engineering and Technology".

Deadline for manuscript submissions: 15 November 2021.

Special Issue Editors
Prof. Dr. Gul N. Khan
Department of Electrical, Computer & Biomedical Engineering, Ryerson
University, Toronto, ON M5B 2K3, Canada
Interests: system-on-a-chip; network-on-a-chip; CPU–GPU-based SoCs; tools and

Dr. Anita Tino
Department of Engineering Science, Simon Fraser University, Burnaby, BC V5A
1S6, Canada
Interests: computing architectures; GPUs; system-on-a-chip; network-on-a-chip;
genomics; ASICs

Special Issue Information

Dear Colleagues,
Advancement in computing system architectures, coupled with the Moore’s Law
and Dennard scaling, has enabled system-on-a-chip (SoC) architects to
accommodate hundreds of processing, memory, and other cores on a single chip.
This complex integration has introduced many challenges in the form of
low-power SoC implementations, and the spread of applications and
computational paradigms including multi- and many-core SoCs, chip
multi-processors (CMPs), and heterogeneous computing. The network-on-a-chip
(NoC) paradigm is based on packet-switched routing mechanism. It can address
most of the on-chip communication problems, including performance limitations
of long interconnects and the integration of many heterogeneous cores on a
chip. NoC has become the most common interconnection structure to integrate
FPGAs, many-core SoCs, and hybrid single-chip systems. However, NoC
performance, hardware cost, and power consumption depend on its various
parameters, such as topology, the number and depth of virtual channels,
routing, and flow control mechanisms.

The goal of this Special Issue is to assemble and put forward innovative ideas
and solutions related to NoC architecture, design, implementation, and
applications. Moreover, the NoCs for FPGAs, multi/many-core SoCs, and
heterogeneous systems will also be explored. Researchers and developers are
invited to submit their unpublished network-on-a-chip-related work. The
extended versions of published papers in conferences, symposiums or workshops
are also welcomed as long as they have substantial (> 40%) additional

Prof. Dr. Gul N. Khan
Dr. Anita Tino
Guest Editors


Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and
logging in to this website. Once you are registered, click here to go to the
submission form. Manuscripts can be submitted until the deadline. All papers
will be peer-reviewed. Accepted papers will be published continuously in the
journal (as soon as accepted) and will be listed together on the special issue
website. Research articles, review articles as well as short communications
are invited. For planned papers, a title and short abstract (about 100 words)
can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under
consideration for publication elsewhere (except conference proceedings
papers). All manuscripts are thoroughly refereed through a single-blind
peer-review process. A guide for authors and other relevant information for
submission of manuscripts is available on the Instructions for Authors page.
Micromachines is an international peer-reviewed open access monthly journal
published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript.
The Article Processing Charge (APC) for publication in this open access
journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted
and use good English. Authors may use MDPI's English editing service prior to
publication or during author revisions.



 * Network-on-a-chip architecture and Implementation
 * NoC topologies, routing, and flow control
 * Modeling, simulation, and synthesis of NoCs
 * Fault tolerance and reliability of networks-on-chip
 * NoCs for FPGAs, CMP, MPSoC, and heterogeneous systems
 * Mapping of applications to NoCs and real NoC case-studies
 * Emerging applications (deep learning) & NoC technologies (optical, wireless)


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