[hpc-announce] AsHES2020 - Tenth International Workshop on, Accelerators and Hybrid Exascale Systems Free Virtual Workshop

[oden]

Call for participation:
The Tenth International Workshop on
Accelerators and Hybrid Exascale Systems
(AsHES) - Virtual Workshop

Due to the COVID-19 situation, this year's AsHES workshop will be held
as a virtual conference.
We invite all interested parties to participate in this workshop.

The participation is free of charge.

Registration and more information under:

https://www.mcs.anl.gov/events/workshops/ashes/2020/index.php


Program
Timezone: CDT (IPDPS New Orleans)

1:25pm Opening Statement (Min Si, Argonne National Laboratory)

Session One: GPU computing (Session Chair: Simon Garcia de Gonzalo,
Barcelona Supercomputing Center)
1:35pm Towards automated kernel selection in machine learning systems: A
SYCL case study (John Lawson)
1:55pm Unified data movement for offloading Charm++ applications   
(Matthias Diener,  Laxmikant Kale),
2:15pm Population Count on Intel CPU, GPU, and FPGA    (Zheming Jin, 
Hal Finkel)
2:45pm SPHYNX: Spectral Partitioning for HYbrid aNd aXelerator-enabled
systems    (Seher Acer,  Erik G. Boman,  Sivasankaran Rajamanickam)

3:15 Break (35 min)

Session Two: FPGAs (Session Chair: Lena Oden, FernUniversität in Hagen)
3:50pm Understanding the Performance of Elementary Numerical Linear
Algebra Kernels in FPGAs (Federico Favaro,  Juan Oliver,  Ernesto
Dufrechou,  Pablo Ezzatti)
4:10pm Scalability of Sparse Matrix Dense Vector Multiply (SpMV) on a
Migrating Thread Architecture    (Brian A. Page, Peter M. Kogge),
4:30pm In-depth Optimization with the OpenACC-to-FPGA Framework on an
Arria X FPGA    (Jacob Lambert, Seyong Lee,  Jeffrey Vetter, Allen Malony)
5:00pm Performance Evaluation of Pipelined Communication Combined with
Computation in OpenCL Programming on FPGA (Norihisa Fujita, Ryohei
Kobayashi, Yoshiki Yamaguchi, Tomohiro Ueno, Kentaro Sano, Taisuke Boku)

5:30pm Keynote:
Taisuke Boku, Center for Computational Sciences, University of Tsukuba:
Multi-Hetero Accelerated Supercomputing: System, Programming and
Applications



Workshop Scope and Goals
========================================
The current computing landscape has gone through an ever-increasing rate
of change and innovation. This change has been driven by the relentless
need to improve the energy-efficient, memory, and compute throughput at
all levels of the architectural hierarchy. Although the amount of data
that has to be organized by today's systems posed new challenges to the
architecture, which can no longer be solved with classical, homogeneous
design.  Improvements in all of those areas have led Heterogeneous
systems to become the norm rather than the exception.

Heterogeneous computing leverages a diverse set of computing (CPU, GPU,
FPGA, TPU ...) and Memory (HBM, Persistent Memory, Coherent PCI
protocols, etc ..),  hierarchical storage systems and units to
accelerate the execution of a diverse set of applications. Emerging and
existing areas such as DeepLearing, BigData, Cloud Computing,
Edge-Computing, Real-time systems, High-Performance Computing and others
have seen a real benefit due to Heterogenous computer architectures.
These new heterogeneous architectures often also require the development
of new applications and programming models, in order to satisfy these
new architectures and to fully utilize these capacities.  This workshop
focuses on understanding the implications of heterogeneous designs at
all levels of the computing system stack, such as hardware, compiler
optimizations, porting of applications, and developing programming
environments for current and emerging systems in all the above-mentioned
areas. It seeks to ground heterogeneous system design research through
studies of application kernels and/or whole applications, as well as
shed light on new tools, libraries and runtime systems that improve the
performance and productivity of applications on heterogeneous systems.

The goal of this workshop is to bring together researchers and
practitioners who are at the forefront of Heterogeneous computing in
order to learn the opportunities and challenges in future Heterogeneous
system design trends and thus help influence the next trends in this area.