[hpc-announce] Call For Papers: 13th International Workshop on Network on Chip Architectures (NoCArc 2020) in Athens, Greece, October 18, 2020

[Mansoor, Naseef]

[Please accept our apologies if you receive multiple copies of this email]

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NoCArc 2020

http://www.nocarc.org/

13th International Workshop on Network on Chip Architectures

October 18, 2020 - Athens, Greece

To be held in conjunction with the
53rd Annual IEEE/ACM International Symposium on Microarchitecture®
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!!! Due to the evolution of the COVID-19 outbreak, it is not still clear if
there will be a virtual event or the conference will be postponed. We are trying
to figure this out as soon as possible. Regardless of the final choice, we will
do our best to make it a safe and fruitful experience. Please visit NoCArc 2020
webpage (http://www.nocarc.org/) for updates. !!!


G E N E R A L  I N F O R M A T I O N

It is well recognized that on-chip communication plays a dominant role in
determining the overall performance, reliability, and energy figures in
many-core architectures. Today, virtually all large-scale chips are designed
on the basis of the Network-on-Chip (NoC). NoCs are now part of a large number
of products that we use every day and this is a proof that NoC paradigm is
scalable and can be adapted to support various computational paradigm,
ranging from multiprocessing to reconfigurable computing and the emerging
area of neuromorphic computing. The goal of NoCArc workshop is to provide a
forum for researchers to present and discuss innovative ideas and solutions
related to the design and implementation of many-core architectures based on
the NoC paradigm.


A R E A S   O F   I N T E R E S T

The workshop will focus on issues related to design, analysis, and testing of
on-chip networks. The topics of specific interest for the workshop include,
but are not limited to:

NoC Architecture and Implementation
  * Topologies, routing, and flow control
  * Managing QoS
  * Reliability issues
  * Security issues
  * Design methodologies and tools

NoC at System-level
  * Design of memory subsystem
  * NoC support for memory and cache access
  * OS support for NoCs
  * Programming models including shared memory, message passing, and novel
    programming models
  * Large-scale systems (datacenters and supercomputers) with NoC-based
    systems as building blocks

NoC Applications
  * Mapping of applications onto NoCs
  * Real and industrial NoC case studies
  * NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
  * NoC designs for heterogeneous systems

NoC Analysis, Optimization, and Verification
  * Power, energy and thermal issues
  * Benchmarking and experience with NoC-based systems
  * Modeling, simulation, and synthesis
  * Verification, debug and test of
  * Metrics and benchmarks

Emerging NoC Technologies
  * Wireless, Optical, and RF
  * NoCs for 3D and 2.5D packages
  * Approximate computing for NoC and NoC-based systems
  * Chip-to-Chip Interconnects

Machine Learning (ML) for NoC-based systems
  * Novel interconnection for machine learning systems
  * Memory access for the NoC-based machine learning system
  * NoC-based machine learning algorithm design


Besides regular papers, papers describing work in progress or incomplete but
sound new innovative ideas related to the workshop theme are also encouraged.


S U B M I S S I O N

Please, visit the workshop webpage (http://www.nocarc.org/) for information
about the submission process.
The accepted conference papers will be invited for an extended journal
version, to be published in a special issue in the MDPI Journal of Low Power
Electronics and Applications (JLPEA, Impact Factor: 1.18)


I M P O R T A N T   D A T E S

* Abstract submission deadline: July 24, 2020
* Paper submission deadline: July 31, 2020
* Acceptance notification: September 1, 2020
* Camera-ready version due: September 8, 2020
* NoCArc workshop: October 18, 2020


O R G A N I Z E R S

GENERAL CHAIR
* Sergi Abadal, Universitat Politècnica de Catalunya, Spain

TPC CHAIRS
* Amlan Ganguly, Rochester Institute of Technology, NY, USA
* Salvatore Monteleone, CY Cergy Paris Université, ENSEA, France

STEERING COMMITTEE
* Maurizio Palesi, Univ. of Catania, Italy
* Davide Patti, Univ. of Catania, Italy
* Masoumeh (Azin) Ebrahimi, KTH Royal Institute of Technology, Sweden
* Masoud Daneshtalab, MDH and KTH, Sweden
* Xiaohang Wang, South China University of Technology, China
* Kun-Chih (Jimmy) Chen, National Sun Yat-sen University, Taiwan