[hpc-announce] Deadline Extension to September 9 for Call for Papers - MCHPC'20 at SC20 Virtual Event: Workshop on Memory Centric High Performance Computing

Yonghong Yan yanyh15 at gmail.com
Wed Aug 26 14:02:00 CDT 2020

                                                Call for Papers

           MCHPC'20: Workshop on Memory Centric High Performance Computing
                 held in conjunction with SC20: The International Conference on
                 High Performance Computing, Networking, Storage and Analysis
                 and in cooperation with IEEE TCHPC

Virtual Event Time/Date: 10:00AM - 6:30PM, U.S. Eastern Standard Time,
Wednesday, November 11, 2020
Virtual Event Info:


                           Submission Deadline Extended: September 9 2020 AOE


The growing disparity between CPU speed and memory speed, known as the
memory wall problem, has been one of the most critical and
long-standing challenges in the computing industry. The situation is
further complicated by the recent expansion of the memory hierarchy,
which is becoming deeper and more diversified with the adoption of new
memory technologies and architectures including 3D-stacked memory,
non-volatile random-access memory (NVRAM), memristor, hybrid software
and hardware caches, etc. Computer architecture and hardware system,
operating systems, storage and file systems, programming stack,
performance model and tools are being enhanced, augmented, or even
redesigned to address the performance, programmability and energy
efficiency challenges of the increasingly complex and heterogeneous
memory systems for HPC and data-intensive applications.

The MCHPC workshop aims to bring together computer and computational
science researchers, from industry, government labs and academia,
concerned with the challenges of efficiently using existing and
emerging memory systems for high performance computing. The term
performance for memory systems is general, which include latency,
bandwidth, power consumption and reliability from the aspect of
hardware memory technologies to what it is manifested in the
application performance. The topics of interest for the MCHPC workshop
include, but are not limited to:

* The challenges and software and hardware solutions of using 3-D
stack memory, NVDIMM, memristor and other processor/compute-in-memory
* Programming interfaces or language extensions that improve the
programmability of using emerging memory technologies and systems.
* Compiler and runtime techniques for optimizing data layout, movement
and consistency enforcement for latency hiding and for improving
bandwidth utilization and energy consumption of memory systems.
* Enhancement or new development for operating systems, storage and
file systems, and I/O systems that address existing and emerging memory
* Modeling, evaluation, and case study of memory system behavior and
application performance that reveals the limitations and characteristics
of existing memory systems.
* Application development and optimization for memory architecture and

Important Dates

* Submission Deadline -- September 9 2020 AoE
* Notifications -- September 30 2020
* Camera Ready Papers -- October 10 2020 (Hard deadline, E-copyright
registration by October 7)
* November 11 2020 - Workshop

 * Yonghong Yan (University of North Carolina at Charlotte, yyan7 at uncc.edu)
 * Ron Brightwell (Sandia National Laboratory, rbbrigh at sandia.gov)
 * Xian-He Sun (Illinois Institute of Technology, sun at iit.edu)
 * Maya B Gokhale (Lawrence Livermore National Laboratory, gokhale2 at llnl.gov)

Program Committee
* Ron Brightwell (Sandia National Laboratory, rbbrigh at sandia.gov)
 * Yonghong Yan (University of North Carolina at Charlotte, yyan7 at uncc.edu)
 * Xian-He Sun (Illinois Institute of Technology)
 * Mingyu Chen (Chinese Academy of Sciences)
 * Bronis R. de Supinski (Lawrence Livermore National Laboratory)
 * Tom Deakin (University of Bristol)
 * Hal Finkel (Argonne National Laboratory and LLVM Foundation)
 * Kyle Hale (Illinois Institute of Technology)
 * Jeff R. Hammond (Intel Corporation)
 * Dong Li (University of California, Merced)
 * Scott Lloyd (Lawrence Livermore National Laboratory)
 * Ivy B. Peng (Lawrence Livermore National Laboratory)
 * Alice Koniges (Univ. of Hawaii, Maui High Performance Computing Center)
 * Arun Rodrigues (Sandia National Laboratory)
 * Chunhua Liao (Lawrence Livermore National Laboratory)

Authors are invited to submit manuscripts in English structured as
technical papers up to 8 pages or as short papers up to 5 pages, both
of letter size (8.5in x 11in) and including figures, tables, and
references. Submissions not conforming to these guidelines may be
returned without review. Your paper should be formatted using IEEE
conference format which can be found from
https://www.ieee.org/conferences/publishing/templates.html. The
workshop also encourages submitters to include transparency and
reproducibility information, using Transparency and Reproducibility
Initiative for SC'20 Technical Papers as guideline.

All manuscripts will be peer-reviewed and judged on correctness,
originality, technical strength, and significance, quality of
presentation, and interest and relevance to the workshop attendees.
Submitted papers must represent original unpublished research that is
not currently under review for any other conference or journal. Papers
not following these guidelines will be rejected without review and
further action may be taken, including (but not limited to)
notifications sent to the heads of the institutions of the authors and
sponsors of the conference. Submissions received after the due date,
exceeding length limit, or not appropriately structured may also not
be considered. At least one author of an accepted paper must register
for and attend the workshop. Authors may contact the workshop
organizers for more information.

Papers should be submitted electronically at:
https://submissions.supercomputing.org/, choose "SC20 Workshop:
MCHPC'20: Workshop on Memory Centric High Performance Computing".

The final papers are planned to be published through IEEE TCHPC.
Published proceedings will be included in the IEEE Xplore digital

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