[hpc-announce] MULTIPROG-2020: The Thirteenth International Workshop on Programmability and Architectures for Heterogeneous Multicores - in conjunction with HiPEAC 2020

[Miquel Pericas]

                              CALL FOR PAPERS

     The Thirteenth International Workshop on Programmability and
         Architectures for Heterogeneous Multicores

                              MULTIPROG-2020

To be held in conjunction with:

the 16th International Conference on
High-Performance and Embedded Architectures and Compilers (HiPEAC)
Bologna, Italy, January 20, 2020

Workshop website: https://sites.google.com/view/multiprog

The ever-increasing number of cores and heterogeneity demanded by AI and
HPC applications has placed new burdens on the programming community.
Software needs to be parallelized and optimized for accelerators such as
GPUs in order to take advantage of the new breed of multi-/many-core
computers. As a result, progress in how to easily harness the computing
power of multi-core architectures is in great demand.

The thirteenth edition of the MULTIPROG workshop aims to bring together
researchers interested in programming models, runtimes, and computer
architecture. The workshop's emphasis is on heterogeneous architectures
and covers issues such as:

-   How can future parallel programming models improve software
     productivity?
-   How should compilers, runtimes and architectures support programming
     models and emerging applications?

MULTIPROG is intended for quick publication of early results,
work-in-progress, etc., and is not intended to prevent later publication
of extended papers. Informal proceedings with accepted papers will be
made available at the workshop and online at the workshop’s web page
https://sites.google.com/view/multiprog

Topics of interest

Papers are sought on topics including, but not limited to:

-   Multi-core architectures
     -   Architectural support for compilers/programming models
     -   Processor (core) architecture and accelerators
     -   Memory system architecture
     -   Performance, power, temperature, and reliability issues
-   Heterogeneous computing
     -   Architectures for heterogeneous systems
     -   Applications for heterogeneous computing
-   Programming models for multi-core and heterogeneous architectures
     -   Language extensions
     -   Run-time systems
     -   Compiler optimizations and techniques
-   Benchmarking of multi-/many-core and heterogeneous architectures
     -   Tools for discovering and understanding parallelism
     -   Tools for understanding performance and debugging
     -   Case studies and performance evaluation

Preliminary dates

-   Submission deadline: November 1, 2019
-   Notification to authors: November 27, 2019

Paper submission

-   Regular research papers: Regular research papers should use LNCS
     format (up to 12 pages, not including references).
-   Short position papers: Short position papers should use LNCS
     format (4-6 pages, not including references). Papers in this
     category should explicitly indicate "Position Paper" as part of the
     title of their manuscript.

The authors of the accepted papers will be requested to provide the
final version of their paper LNCS format. Please use the templates
below:

-   LNCS Latex template:
ftp://ftp.springernature.com/cs-proceeding/llncs/llncs2e.zip
-   LNCS Word template:
ftp://ftp.springernature.com/cs-proceeding/llncs/word/splnproc1703.zip

Submission link: https://easychair.org/conferences/?conf=multiprog2020

Program Committee

-   Christos Kotselidis, University of Manchester
-   Hans Vandierendonck, Queen’s University of Technology of Belfast
-   Pedro Trancoso, Chalmers University of Technology
-   Sasa Tomic, IBM Research
-   Trevor Carlson, NU Singapore
-   Vasilis Karakostas, NTUA
-   Avi Mendelson, Technion
-   Magnus Jahre, NTNU

Organizers

-   Miquel Pericàs, miquelp at chalmers.se, Chalmers University of Technology
-   Oscar Palomar, oscar.palomar at bsc.es, Barcelona Supercomputing Center
-   Vassilis Papaefstathiou, papaef at ics.forth.gr, FORTH-ICS