[hpc-announce] DEADLINE EXTENDED: AccML'20 - HiPEAC Workshop on Accelerated Machine Learning 2020

[Jose Cano Reyes]

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Workshop on Accelerated Machine Learning (AccML)

Co-located with the HiPEAC 2020 Conference
(https://www.hipeac.net/2020/bologna/)

January 20, 2020
Bologna, Italy
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       UPDATE: DEADLINE EXTENSION TO NOVEMBER 22, 2019

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CALL FOR CONTRIBUTIONS
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In the last 5 years, the remarkable performance achieved in a variety of 
application areas (natural language processing, computer vision, games, 
etc.) has led to the emergence of heterogeneous architectures to 
accelerate machine learning workloads. In parallel, production 
deployment, model complexity and diversity pushed for higher 
productivity systems, more powerful programming abstractions, software 
and system architectures, dedicated runtime systems and numerical 
libraries, deployment and analysis tools. Deep learning models are 
generally memory and computationally intensive, for both training and 
inference. Accelerating these operations has obvious advantages, first 
by reducing the energy consumption (e.g. in data centers), and secondly, 
making these models usable on smaller devices at the edge of the 
Internet. In addition, while convolutional neural networks have 
motivated much of this effort, numerous applications and models involve 
a wider variety of operations, network architectures, and data 
processing. These applications and models permanently challenge computer 
architecture, the system stack, and programming abstractions. The high 
level of interest in these areas calls for a dedicated forum to discuss 
emerging acceleration techniques and computation paradigms for machine 
learning algorithms, as well as the applications of machine learning to 
the construction of such systems.


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Links to the Workshop pages
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HiPEAC: https://www.hipeac.net/2020/bologna/#/schedule/sessions/7739/

Organizers: http://workshops.inf.ed.ac.uk/accml/


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Speakers
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* Keynote speaker: Luca Benini (ETH Zurich and U. di Bologna)

Title: Extreme Edge AI on Open Hardware

Abstract: Edge Artificial Intelligence (AI) is the new mega-trend, as 
privacy concerns and network bandwidth/latency bottlenecks prevent cloud 
offloading of AI functions in many application domains, from autonomous 
driving to advanced prosthetics. Hence we need to push AI toward sensors 
and actuators. I will give an overview of recent efforts in developing 
systems of-on-chips based on open source hardware and  capable of 
significant analytics and AI functions "at the extreme edge", i.e. 
within the limited power budget of traditional microcontrollers that can 
be co-located and integrated with the sensors/actuators themselves.  
These open, extreme edge AI platforms create an exciting playground for 
research and innovation.

Bio: Luca Benini holds the chair of digital Circuits and systems at ETHZ 
and is Full Professor at the Universita di Bologna. He received a PhD 
from Stanford University. In 2009-2012 he served as chief architect in 
STmicroelectronics France.  Dr. Benini's research interests are in 
energy-efficient computing systems design, from embedded to 
high-performance. He is also active in the design of ultra-low power 
VLSI Circuits and smart sensing micro-systems. He has published more 
than 1000 peer-reviewed papers and five books. He is an ERC-advanced 
grant winner, a Fellow of the IEEE, of the ACM and a member of the 
Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van 
Valkenburg award and of the  2019 IEEE TCAD Donald O. Pederson Best 
Paper Award.

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* Invited speaker: Carole-Jean Wu (Facebook AI, Arizona State University)

Title: Machine Learning at Scale

Abstract: Machine learning systems are being widely deployed in 
production datacenter infrastructure and over billions of edge devices. 
This talk seeks to address key system design challenges when scaling 
machine learning solutions to billions of people. What are key 
similarities and differences between cloud and edge infrastructure? The 
talk will conclude with open system research directions for deploying 
machine learning at scale.

Bio: Carole-Jean Wu is a Research Scientist at Facebook’s AI 
Infrastructure Research. She is also a tenured Associate Professor of 
CSE in Arizona State University. Carole-Jean’s research focuses in 
Computer and System Architectures. More recently, her research has 
pivoted into designing systems for machine learning. She is the leading 
author of “Machine Learning at Facebook: Understanding Inference at the 
Edge” that presents unique design challenges faced when deploying ML 
solutions at scale to the edge, from over billions of smartphones to 
Facebook’s virtual reality platforms. Carole-Jean received her Ph.D. and 
M.A. from Princeton and B.Sc. from Cornell.

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* Invited speaker: Albert Cohen (Google, Paris)

Title: Abstractions, Algorithms and Infrastructure for Post-Moore 
Optimizing Compilers

Abstract: MLIR is a recently announced open source infrastructure to 
accelerate innovation in machine learning (ML) and high-performance 
computing (HPC). It addresses the growing software and hardware 
fragmentation across machine learning frameworks, enabling machine 
learning models to be consistently represented and executed on any type 
of hardware. It also unifies graph representations and operators for ML 
and HPC. It facilitates the design and implementation of code 
generators, translators and optimizations at different levels of 
abstraction and also across application domains, hardware targets and 
execution environments. We will share our vision, progress and plans in 
the MLIR project, zooming in on graph-level and loop nest optimization 
as illustrative examples.

Bio: Albert Cohen is a research scientist at Google. He worked as a 
research scientist at Inria from 2000 to 2018. He graduated from École 
Normale Supérieure de Lyon and received his PhD from the University of 
Versailles in 1999 (awarded two national prizes). He has also been a 
visiting scholar at the University of Illinois, an invited professor at 
Philips Research, and a visiting scientist at Facebook Artificial 
Intelligence Research. Albert Cohen works on parallelizing and 
optimizing compilers, parallel programming languages and systems, and 
synchronous programming for reactive control systems. He served as the 
general or program chair of some of the main conferences in the area and 
a member of the editorial board of two journals. He co-authored more 
than 180 peer-reviewed papers and has been the advisor for 26 PhD 
theses. Several research projects led by Albert Cohen resulted in 
effective transfer to production compilers and programming environments.

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* Invited speaker: Rune Holm (Arm)

Title: Big neural networks in small spaces; Towards end-to-end 
optimisation for ML at the edge

Abstract: Neural networks have taken over use case after use case, from 
image recognition, speech recognition, image enhancement to driving 
cars, and show no sign of letting up. Yet so many of these use cases are 
done by acquiring data and sending it off to the cloud for inference. 
On-device ML brings unprecedented capabilities and opportunities to edge 
devices with improved privacy, security, and reliability. This talk 
explores the many aspects of system optimisation for edge ML, from 
training-time optimisation, to the compilation of neural networks, to 
the design of machine learning hardware, and looks at ways to save 
execution time and memory footprint while preserving accuracy.

Bio: Rune Holm has been part of the semiconductor industry for more than 
a decade. He started out on Mali GPUs, doing GPU microarchitecture and 
designing shader compilers for VLIW cores. He then moved on to research 
into experimental GPGPU designs and architectures targeting HPC, machine 
learning and computer vision. He’s currently part of the Arm Machine 
Learning Group, focusing on neural network accelerator architecture and 
compilers optimising for these designs.


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Topics
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Topics of interest include (but are not limited to):

- Novel ML systems?: heterogeneous multi/many-core systems, GPUs, FPGAs;
- Software ML acceleration: languages, primitives, libraries, compilers 
and frameworks;
- Novel ML hardware accelerators and associated software;
- Emerging semiconductor technologies with applications to ML hardware 
acceleration;
- ML for the construction and tuning of systems;
- Cloud and edge ML computing: hardware and software to accelerate 
training and inference;
- Computing systems research addressing the privacy and security of 
ML-dominated systems.


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Submission
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Papers will be reviewed by the workshop's technical program committee 
according to criteria regarding a submission's quality, relevance to the 
workshop's topics, and, foremost, its potential to spark discussions 
about directions, insights, and solutions in the context of accelerating 
machine learning. Research papers, case studies, and position papers are 
all welcome.
In particular, we encourage authors to submit works-In-Progress papers: 
To facilitate sharing of thought-provoking ideas and high-potential 
though preliminary research, authors are welcome to make submissions 
describing early-stage, in-progress, and/or exploratory work in order to 
elicit feedback, discover collaboration opportunities, and generally 
spark discussion.

The workshop does not have formal proceedings.


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Important Dates
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Submission deadline: November 22, 2019
Notification of decision: December 6, 2019


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Organizers
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José Cano (University of Glasgow)
Valentin Radu (University of Edinburgh)
Marco Cornero (DeepMind)
Albert Cohen (Google)
Olivier Temam (DeepMind)
Alex Ramirez (Google)